[gcc(refs/users/meissner/heads/work144-vsize)] Update ChangeLog.*

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:107a6e004e5fac7caa42aea659f1f8f8046e5ea2

commit 107a6e004e5fac7caa42aea659f1f8f8046e5ea2
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Nov 15 13:34:57 2023 -0500

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.vsize | 163 +++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 162 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.vsize b/gcc/ChangeLog.vsize
index a1aeb7b3527..eff3cb95398 100644
--- a/gcc/ChangeLog.vsize
+++ b/gcc/ChangeLog.vsize
@@ -1,3 +1,164 @@
+==================== Branch work144-vsize, patch #401 ====================
+
+Add init, extract, and set support for vector pair modes.
+
+2023-11-15  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vector.md (VEC_E): Add vector pair modes.
+	(VEC_base_l): Likewise.
+
+==================== Branch work144-vsize, patch #400 ====================
+
+Add support for -mvector-size-32.
+
+2023-11-09  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/predicates.md (const_0_to_31_operand): New predicate.
+	* config/rs6000/rs6000-c.cc (rs6000_cpu_cpp_builtins): Define
+	__VECTOR_SIZE_32__ if -mvector-size-32 was used.
+	* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
+	-mvector-size-32.
+	(POWERPC_MASKS): Likewise.
+	* config/rs6000/rs6000-protos.h (vector_pair_to_vector_mode): New
+	declaration.
+	(rs6000_adjust_for_vector_pair): Likewise.
+	(split_unary_vector_pair): Likewise.
+	(split_binary_vector_pair): Likewise.
+	(split_fma_vector_pair): Likewise.
+	* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
+	support for 32-byte vector types created with -mvector-size-32.
+	(rs6000_modes_tieable_p): Make all 32-byte vectors tie with other
+	32-byte vectors.
+	(rs6000_debug_reg_global): If -mdebug=reg, print whether
+	-mvector-size-32 was enabled.
+	(rs6000_init_hard_regno_mode_ok): Add support for 32-byte vectors.
+	(rs6000_option_override_internal): Add checking for -mvector-size-32.
+	(rs6000_opt_masks): Add -mvector-size-32.
+	(rs6000_expand_vector_extract): Add support for 32-byte vectors.
+	(reg_offset_addressing_ok_p): Likewise.
+	(rs6000_emit_move): Likewise.
+	(rs6000_preferred_reload_class): Likewise.
+	(vector_pair_to_vector_mode): New vector pair helper function.
+	(rs6000_adjust_for_vector_pair): Likewise.
+	(rs6000_split_vpair_constan): Likewise.
+	(split_unary_vector_pair): Likewise.
+	(split_binary_vector_pair): Likewise.
+	(split_fma_vector_pair): Likewise.
+	(rs6000_split_multireg_move): Add support for 32-byte vectors.
+	* config/rs6000/rs6000.h (VECTOR_PAIR_MODE): New macro.
+	* config/rs6000/rs6000.md (wd attribute): Add 32-byte vector modes.
+	(RELOAD): Likewise.
+	(toplevel): Include vector-pair.md.
+	* config/rs6000/rs6000.opt (-mvector-size-32): New option.
+	* config/rs6000/t-rs6000 (MD_INCLUDES): Add vector-pair.md.
+	* config/rs6000/vector-pair.md: New file.
+	* config/rs6000/vector.md (VEC_base): Add 32-byte vector modes.
+	* config/rs6000/vsx.md (VSX_EXTRACT_PREDICATE): Likewise.
+	(VSX_EX): Likewise.
+	(VPAIR_V4DI_V4DF): New mode iterator.
+	(VPAIR_VECTOR): New mode attribute.
+	(vpair_vector): Likewise.
+	(vsx_extract_<mode>, VPAIR_V4DF_V4DI iterator): New extract insn for
+	vector pair support.
+	(vsx_extract_v8sf): Likewise.
+	(vsx_extract_<mode>, VPAIR_SMALL_INT iterator): Likewise.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vector-size-32-1.c: New test.
+	* gcc.target/powerpc/vector-size-32-2.c: New test.
+	* gcc.target/powerpc/vector-size-32-3.c: New test.
+	* gcc.target/powerpc/vector-size-32-4.c: New test.
+	* gcc.target/powerpc/vector-size-32-5.c: New test.
+	* gcc.target/powerpc/vector-size-32-6.c: New test.
+
+
 ==================== Branch work144-vsize, patch #1 (from work144) ====================
 
-See ChangeLog.meissner
+Power10: Add options to disable load and store vector pair.
+
+This is version 2 of the patch to add -mno-load-vector-pair and
+-mno-store-vector-pair undocumented tuning switches.
+
+The differences between the first version of the patch and this version is that
+I added explicit RTL abi attributes for when the compiler can generate the load
+vector pair and store vector pair instructions.  By having this attribute, the
+movoo insn has separate alternatives for when we generate the instruction and
+when we want to split the instruction into 2 separate vector loads or stores.
+
+In the first version of the patch, I had previously provided built-in functions
+that would always generate load vector pair and store vector pair instructions
+even if these instructions are normally disabled.  I found these built-ins
+weren't specified like the other vector pair built-ins, and I didn't include
+documentation for the built-in functions.  If we want such built-in functions,
+we can add them as a separate patch later.
+
+In addition, since both versions of the patch adds #pragma target and attribute
+support to change the results for individual functions, we can select on a
+function by function basis what the defaults for load/store vector pair is.
+
+The original text for the patch is:
+
+In working on some future patches that involve utilizing vector pair
+instructions, I wanted to be able to tune my program to enable or disable using
+the vector pair load or store operations while still keeping the other
+operations on the vector pair.
+
+This patch adds two undocumented tuning options.  The -mno-load-vector-pair
+option would tell GCC to generate two load vector instructions instead of a
+single load vector pair.  The -mno-store-vector-pair option would tell GCC to
+generate two store vector instructions instead of a single store vector pair.
+
+If either -mno-load-vector-pair is used, GCC will not generate the indexed
+stxvpx instruction.  Similarly if -mno-store-vector-pair is used, GCC will not
+generate the indexed lxvpx instruction.  The reason for this is to enable
+splitting the {,p}lxvp or {,p}stxvp instructions after reload without needing a
+scratch GPR register.
+
+The default for -mcpu=power10 is that both load vector pair and store vector
+pair are enabled.
+
+I added code so that the user code can modify these settings using either a
+'#pragma GCC target' directive or used __attribute__((__target__(...))) in the
+function declaration.
+
+I added tests for the switches, #pragma, and attribute options.
+
+I have built this on both little endian power10 systems and big endian power9
+systems doing the normal bootstrap and test.  There were no regressions in any
+of the tests, and the new tests passed.  Can I check this patch into the master
+branch?
+
+2023-11-09  Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/mma.md (movoo): Add support for -mno-load-vector-pair and
+	-mno-store-vector-pair.
+	* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add support for
+	-mload-vector-pair and -mstore-vector-pair.
+	(POWERPC_MASKS): Likewise.
+	* config/rs6000/rs6000.cc (rs6000_setup_reg_addr_masks): Only allow
+	indexed mode for OOmode if we are generating both load vector pair and
+	store vector pair instructions.
+	(rs6000_option_override_internal): Add support for -mno-load-vector-pair
+	and -mno-store-vector-pair.
+	(rs6000_opt_masks): Likewise.
+	* config/rs6000/rs6000.md (isa attribute): Add lxvp and stxvp
+	attributes.
+	(enabled attribute): Likewise.
+	* config/rs6000/rs6000.opt (-mload-vector-pair): New option.
+	(-mstore-vector-pair): Likewise.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vector-pair-attribute.c: New test.
+	* gcc.target/powerpc/vector-pair-pragma.c: New test.
+	* gcc.target/powerpc/vector-pair-switch1.c: New test.
+	* gcc.target/powerpc/vector-pair-switch2.c: New test.
+	* gcc.target/powerpc/vector-pair-switch3.c: New test.
+	* gcc.target/powerpc/vector-pair-switch4.c: New test.