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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work144-vsize)] Rework vector pair init, stub vector pair set and extract.
Date: Thu, 16 Nov 2023 17:46:50 +0000 (GMT) [thread overview]
Message-ID: <20231116174650.E15403858C66@sourceware.org> (raw)
https://gcc.gnu.org/g:a75492f1cf3b1f568414da4fac39b28b9623057f
commit a75492f1cf3b1f568414da4fac39b28b9623057f
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Nov 16 12:46:29 2023 -0500
Rework vector pair init, stub vector pair set and extract.
2023-11-16 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000-protos.h (rs6000_expand_vector_pair_init): New
declaration.
(rs6000_expand_vector_pair_set): Likewise.
(rs6000_expand_vector_pair_extract): Likewise.
* config/rs6000/rs6000.cc (rs6000_expand_vector_init): Remove vector
pair code.
(rs6000_expand_vector_pair_init): New function.
(rs6000_expand_vector_pair_set): New stub function.
(rs6000_expand_vector_extract): Remove vector pair support.
(rs6000_expand_vector_pair_extract): New stub function.
* config/rs6000/vector-pair.md (vpair_element_l): Return correct types.
(vec_init<mode><vpair_element_l>): New insn.
(vec_set<mode>): Likewise.
(vec_extract<mode><vpair_element_l): Likewise.
* config/rs6000/vector.md (VEC_E): Remvoe vector pair support.
(VEC_base): Likewise.
(VEC_base_l): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-protos.h | 3 ++
gcc/config/rs6000/rs6000.cc | 111 ++++++++++++++++++++++++++++----------
gcc/config/rs6000/vector-pair.md | 34 +++++++++++-
gcc/config/rs6000/vector.md | 13 +----
4 files changed, 120 insertions(+), 41 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index b260fe31180..af5c2ebd822 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -61,8 +61,11 @@ extern bool rs6000_move_128bit_ok_p (rtx []);
extern bool rs6000_split_128bit_ok_p (rtx []);
extern void rs6000_expand_float128_convert (rtx, rtx, bool);
extern void rs6000_expand_vector_init (rtx, rtx);
+extern void rs6000_expand_vector_pair_init (rtx, rtx);
extern void rs6000_expand_vector_set (rtx, rtx, rtx);
+extern void rs6000_expand_vector_pair_set (rtx, rtx, rtx);
extern void rs6000_expand_vector_extract (rtx, rtx, rtx);
+extern void rs6000_expand_vector_pair_extract (rtx, rtx, rtx);
extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx);
extern rtx rs6000_adjust_vec_address (rtx, rtx, rtx, rtx, machine_mode);
extern void altivec_expand_vec_perm_le (rtx op[4]);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 663f12b8449..da96359474f 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7103,19 +7103,6 @@ rs6000_expand_vector_init (rtx target, rtx vals)
}
}
- /* Handle vector pair splats. */
- if (all_same && mode == V4DFmode)
- {
- emit_insn (gen_vpair_splat_v4df (target, XVECEXP (vals, 0, 0)));
- return;
- }
-
- if (all_same && mode == V8SFmode)
- {
- emit_insn (gen_vpair_splat_v8sf (target, XVECEXP (vals, 0, 0)));
- return;
- }
-
/* Store value to stack temp. Load vector element. Splat. However, splat
of 64-bit items is not supported on Altivec. */
if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
@@ -7330,6 +7317,72 @@ rs6000_expand_vector_init (rtx target, rtx vals)
emit_move_insn (target, mem);
}
+/* Initialize vector pair TARGET to VALS. */
+
+void
+rs6000_expand_vector_pair_init (rtx target, rtx vals)
+{
+ machine_mode mode_vpair = GET_MODE (target);
+ machine_mode mode_vector;
+ size_t n_elts_vpair = GET_MODE_NUNITS (mode_vpair);
+ size_t n_elts_vector = n_elts_vpair / 2;
+ bool all_same = true;
+ rtx first = XVECEXP (vals, 0, 0);
+ rtx (*gen_splat) (rtx, rtx);
+ rtx (*gen_assemble) (rtx, rtx, rtx);
+
+ switch (mode_vpair)
+ {
+ case E_V4DFmode:
+ mode_vector = V2DFmode;
+ gen_splat = gen_vpair_splat_v4df;
+ gen_assemble = gen_vpair_assemble_v4df;
+ break;
+
+ case E_V8SFmode:
+ mode_vector = V8SFmode;
+ gen_splat = gen_vpair_splat_v8sf;
+ gen_assemble = gen_vpair_assemble_v8sf;
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+
+ /* See if we can do a splat operation. */
+ for (size_t i = 1; i < n_elts_vpair; ++i)
+ {
+ if (!rtx_equal_p (XVECEXP (vals, 0, i), first))
+ {
+ all_same = false;
+ break;
+ }
+ }
+
+ if (all_same)
+ {
+ emit_insn (gen_splat (target, first));
+ return;
+ }
+
+ /* Break the initialization into two parts. */
+ rtx vector_hi = gen_reg_rtx (mode_vector);
+ rtx vector_lo = gen_reg_rtx (mode_vector);
+ rtvec vals_hi = rtvec_alloc (n_elts_vector);
+ rtvec vals_lo = rtvec_alloc (n_elts_vector);
+
+ for (size_t i = 0; i < n_elts_vector; i++)
+ {
+ RTVEC_ELT (vals_hi, i) = XVECEXP (vals, 0, i);
+ RTVEC_ELT (vals_lo, i) = XVECEXP (vals, 0, i + n_elts_vector);
+ }
+
+ rs6000_expand_vector_init (vector_hi, gen_rtx_CONST_VECTOR (mode_vector, vals_hi));
+ rs6000_expand_vector_init (vector_lo, gen_rtx_CONST_VECTOR (mode_vector, vals_lo));
+ emit_insn (gen_assemble (target, vector_hi, vector_lo));
+ return;
+}
+
/* Insert VAL into IDX of TARGET, VAL size is same of the vector element, IDX
is variable and also counts by vector element size for p9 and above. */
@@ -7658,6 +7711,15 @@ rs6000_expand_vector_set (rtx target, rtx val, rtx elt_rtx)
emit_insn (gen_rtx_SET (target, x));
}
+/* Set field ELT_RTX of vaector pair TARGET to VAL. */
+
+void
+rs6000_expand_vector_pair_set (rtx target, rtx val, rtx elt_rtx)
+{
+ if (target || val || elt_rtx)
+ gcc_unreachable ();
+}
+
/* Extract field ELT from VEC into TARGET. */
void
@@ -7708,20 +7770,6 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
return;
}
break;
- case E_V4DFmode:
- if (TARGET_MMA && TARGET_VECTOR_SIZE_32)
- {
- emit_insn (gen_vsx_extract_v4df (target, vec, elt));
- return;
- }
- break;
- case E_V8SFmode:
- if (TARGET_MMA && TARGET_VECTOR_SIZE_32)
- {
- emit_insn (gen_vsx_extract_v8sf (target, vec, elt));
- return;
- }
- break;
}
}
else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
@@ -7798,6 +7846,15 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
}
}
+/* Extract field ELT from VEC into TARGET. */
+
+void
+rs6000_expand_vector_pair_extract (rtx target, rtx vec, rtx elt)
+{
+ if (target || vec || elt)
+ gcc_unreachable ();
+}
+
/* Return the offset within a memory object (MEM) of a vector type to a given
element within the vector (ELEMENT) with an element size (SCALAR_SIZE). If
the element is constant, we return a constant integer.
diff --git a/gcc/config/rs6000/vector-pair.md b/gcc/config/rs6000/vector-pair.md
index 0e74da1de66..13fcb5e3d01 100644
--- a/gcc/config/rs6000/vector-pair.md
+++ b/gcc/config/rs6000/vector-pair.md
@@ -63,8 +63,8 @@
(V4DF "DF")])
;; Map vector pair mode to the base element mode in lower case.
-(define_mode_attr vpair_element_l [(V8SF "v4sf")
- (V4DF "v2df")])
+(define_mode_attr vpair_element_l [(V8SF "sf")
+ (V4DF "df")])
;; Vector pair move support.
(define_expand "mov<mode>"
@@ -117,6 +117,36 @@
(set_attr "length" "*,8,*,8,8,8")
(set_attr "isa" "lxvp,*,stxvp,*,*,*")])
\f
+;; Vector initialization, set, extract
+(define_expand "vec_init<mode><vpair_element_l>"
+ [(match_operand:VPAIR 0 "vlogical_operand")
+ (match_operand:VPAIR 1 "")]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+{
+ rs6000_expand_vector_pair_init (operands[0], operands[1]);
+ DONE;
+})
+
+(define_expand "vec_set<mode>"
+ [(match_operand:VPAIR 0 "vlogical_operand")
+ (match_operand:<VPAIR_ELEMENT> 1 "register_operand")
+ (match_operand 2 "vec_set_index_operand")]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+{
+ rs6000_expand_vector_pair_set (operands[0], operands[1], operands[2]);
+ DONE;
+})
+
+(define_expand "vec_extract<mode><vpair_element_l>"
+ [(match_operand:<VPAIR_ELEMENT> 0 "register_operand")
+ (match_operand:VPAIR 1 "vlogical_operand")
+ (match_operand 2 "const_int_operand")]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+{
+ rs6000_expand_vector_pair_extract (operands[0], operands[1], operands[2]);
+ DONE;
+})
+
;; Assemble a vector pair from two vectors. Unlike
;; __builtin_mma_assemble_pair, this function produces a vector pair output
;; directly and it takes all of the vector types.
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 94b5349eac7..f4fc620b653 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -62,14 +62,7 @@
(define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF V1TI])
;; Vector init/extract modes
-(define_mode_iterator VEC_E [V16QI
- V8HI
- V4SI
- V2DI
- V4SF
- V2DF
- (V8SF "TARGET_MMA && TARGET_VECTOR_SIZE_32")
- (V4DF "TARGET_MMA && TARGET_VECTOR_SIZE_32")])
+(define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
;; Vector modes for 64-bit base types
(define_mode_iterator VEC_64 [V2DI V2DF])
@@ -82,9 +75,7 @@
(V8HI "HI")
(V4SI "SI")
(V2DI "DI")
- (V8SF "SF")
(V4SF "SF")
- (V4DF "DF")
(V2DF "DF")
(V1TI "TI")
(TI "TI")])
@@ -94,9 +85,7 @@
(V8HI "hi")
(V4SI "si")
(V2DI "di")
- (V8SF "sf")
(V4SF "sf")
- (V4DF "df")
(V2DF "df")
(V1TI "ti")
(TI "ti")])
reply other threads:[~2023-11-16 17:46 UTC|newest]
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