[gcc(refs/users/meissner/heads/work144-vsize)] Rework vector pair extract.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:1c7a497482f216a5a98e366b3157eb824601722c

commit 1c7a497482f216a5a98e366b3157eb824601722c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Nov 16 15:15:41 2023 -0500

    Rework vector pair extract.
    
    2023-11-16  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000-protos.h (rs6000_expand_vector_pair_extract):
            Delete.
            * config/rs6000/rs6000.cc (rs6000_expand_vector_pair_extract): Delete.
            * config/rs6000/vector-pair.md (vec_extract<mode><vpair_element_l>): Rework.

Diff:
---
 gcc/config/rs6000/rs6000-protos.h |  1 -
 gcc/config/rs6000/rs6000.cc       |  9 ---------
 gcc/config/rs6000/vector-pair.md  | 29 +++++++++++++++++++++++------
 3 files changed, 23 insertions(+), 16 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index af5c2ebd822..b0fde773e33 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -65,7 +65,6 @@ extern void rs6000_expand_vector_pair_init (rtx, rtx);
 extern void rs6000_expand_vector_set (rtx, rtx, rtx);
 extern void rs6000_expand_vector_pair_set (rtx, rtx, rtx);
 extern void rs6000_expand_vector_extract (rtx, rtx, rtx);
-extern void rs6000_expand_vector_pair_extract (rtx, rtx, rtx);
 extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx);
 extern rtx rs6000_adjust_vec_address (rtx, rtx, rtx, rtx, machine_mode);
 extern void altivec_expand_vec_perm_le (rtx op[4]);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index da96359474f..5058ed06347 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7846,15 +7846,6 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
     }
 }
 
-/* Extract field ELT from VEC into TARGET.  */
-
-void
-rs6000_expand_vector_pair_extract (rtx target, rtx vec, rtx elt)
-{
-  if (target || vec || elt)
-    gcc_unreachable ();
-}
-
 /* Return the offset within a memory object (MEM) of a vector type to a given
    element within the vector (ELEMENT) with an element size (SCALAR_SIZE).  If
    the element is constant, we return a constant integer.
diff --git a/gcc/config/rs6000/vector-pair.md b/gcc/config/rs6000/vector-pair.md
index 13fcb5e3d01..d83bdcb209b 100644
--- a/gcc/config/rs6000/vector-pair.md
+++ b/gcc/config/rs6000/vector-pair.md
@@ -117,7 +117,7 @@
    (set_attr "length" "*,8,*,8,8,8")
    (set_attr "isa" "lxvp,*,stxvp,*,*,*")])
 \f
-;; Vector initialization, set, extract
+;; Vector pair initialization
 (define_expand "vec_init<mode><vpair_element_l>"
   [(match_operand:VPAIR 0 "vlogical_operand")
    (match_operand:VPAIR 1 "")]
@@ -127,6 +127,7 @@
   DONE;
 })
 
+;; Vector pair set element
 (define_expand "vec_set<mode>"
   [(match_operand:VPAIR 0 "vlogical_operand")
    (match_operand:<VPAIR_ELEMENT> 1 "register_operand")
@@ -137,13 +138,29 @@
   DONE;
 })
 
-(define_expand "vec_extract<mode><vpair_element_l>"
-  [(match_operand:<VPAIR_ELEMENT> 0 "register_operand")
-   (match_operand:VPAIR 1 "vlogical_operand")
-   (match_operand 2 "const_int_operand")]
+;; Vector pair extraction
+(define_insn_and_split "vec_extract<mode><vpair_element_l>"
+  [(set (match_operand:<VPAIR_ELEMENT> 0 "vsx_register_operand" "=wa")
+	(vec_select:<VPAIR_ELEMENT>
+	 (match_operand:VPAIR 1 "vsx_register_operand" "wa")
+	 (parallel [(match_operand:QI 2 "const_int_operand" "n")])))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
 {
-  rs6000_expand_vector_pair_extract (operands[0], operands[1], operands[2]);
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+  HOST_WIDE_INT elt = INTVAL (operands[2]);
+  machine_mode mode = <MODE>mode;
+  machine_mode vmode = <VPAIR_VECTOR>mode;
+  unsigned vsize = GET_MODE_SIZE (<VPAIR_VECTOR>mode);
+  unsigned reg_num = ((WORDS_BIG_ENDIAN && elt >= vsize)
+		      || (!WORDS_BIG_ENDIAN && elt < vsize));
+	   
+  rtx vreg = simplify_gen_subreg (vmode, op1, mode, reg_num * 16);
+  emit_insn (gen_vsx_extract_<vpair_vector_l> (op0, vreg,
+					       GEN_INT (elt % vsize)));
   DONE;
 })