From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 8ACE13858C2B; Thu, 16 Nov 2023 22:01:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8ACE13858C2B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1700172076; bh=2K9aIxbfPwCZ64m70wDr3YVdK9CYWftLs46r2COJOlg=; h=From:To:Subject:Date:From; b=KBzxq9naM2PS6g84Zk6LxDzJkb8HvR/kNz6Ajfr7dF9llr0wnEeTZxR+x3eBvcx4R 25FZqWXjxEsgyCYuUPUWtLGGEljDMP5fMCE0X1aeHtODfiVNxF7febFs5jSeeSX7NS okON+ukdFUAu5l8ISbFQPc9l51LJjlQ6M2n61TWk= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work144-vsize)] Convert -mvector-size-32 to variable, not mask. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work144-vsize X-Git-Oldrev: aaceaec031461914957ecd65423a58bfa3202a92 X-Git-Newrev: a1e4b290bc84c59989863b6f61a68200aaaf7904 Message-Id: <20231116220116.8ACE13858C2B@sourceware.org> Date: Thu, 16 Nov 2023 22:01:16 +0000 (GMT) List-Id: https://gcc.gnu.org/g:a1e4b290bc84c59989863b6f61a68200aaaf7904 commit a1e4b290bc84c59989863b6f61a68200aaaf7904 Author: Michael Meissner Date: Thu Nov 16 17:00:53 2023 -0500 Convert -mvector-size-32 to variable, not mask. 2023-11-16 Michael Meissner gcc/ * config/rs6000/rs6000-c.cc (rs6000_cpu_cpp_builtins): Check for -mmma as well as -mvector-size-32. * config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Convert -mvector-size-32 to variable. (POWERPOC_MASKS): Likewise. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Likewise. (rs6000_opt_masks): Likewise. (rs6000_opt_vars): Likewise. * config/rs6000/rs6000.opt (-mvector-size-32): Likewise. Diff: --- gcc/config/rs6000/rs6000-c.cc | 2 +- gcc/config/rs6000/rs6000-cpus.def | 4 +--- gcc/config/rs6000/rs6000.cc | 8 +++++--- gcc/config/rs6000/rs6000.opt | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 24f90195985..27114b14022 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -631,7 +631,7 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile) builtin_define ("__SIZEOF_IBM128__=16"); if (ieee128_float_type_node) builtin_define ("__SIZEOF_IEEE128__=16"); - if (TARGET_VECTOR_SIZE_32) + if (TARGET_MMA && TARGET_VECTOR_SIZE_32) builtin_define ("__VECTOR_SIZE_32__"); #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 4f12a805ef3..75435a52d1a 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -82,8 +82,7 @@ | OPTION_MASK_PCREL \ /* | OPTION_MASK_PCREL_OPT */ \ | OPTION_MASK_PREFIXED \ - | OPTION_MASK_STORE_VECTOR_PAIR \ - | OPTION_MASK_VECTOR_SIZE_32) + | OPTION_MASK_STORE_VECTOR_PAIR) #define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \ | OPTION_MASK_POWER10 \ @@ -162,7 +161,6 @@ | OPTION_MASK_SOFT_FLOAT \ | OPTION_MASK_STORE_VECTOR_PAIR \ | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ - | OPTION_MASK_VECTOR_SIZE_32 \ | OPTION_MASK_VSX) #endif diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 5058ed06347..23276f2c92f 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4464,11 +4464,11 @@ rs6000_option_override_internal (bool global_init_p) if (!TARGET_MMA && TARGET_VECTOR_SIZE_32) { - if ((rs6000_isa_flags_explicit & OPTION_MASK_STORE_VECTOR_PAIR) != 0) + if (OPTION_SET_P (TARGET_VECTOR_SIZE_32)) warning (0, "%qs should not be used unless you use %qs", "-mvector-size-32", "-mmma"); - rs6000_isa_flags &= OPTION_MASK_VECTOR_SIZE_32; + TARGET_VECTOR_SIZE_32 = 0; } /* Enable power10 fusion if we are tuning for power10, even if we aren't @@ -24610,7 +24610,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "store-vector-pair", OPTION_MASK_STORE_VECTOR_PAIR, false, true }, { "string", 0, false, true }, { "update", OPTION_MASK_NO_UPDATE, true , true }, - { "vector-size-32", OPTION_MASK_VECTOR_SIZE_32, false, true }, { "vsx", OPTION_MASK_VSX, false, true }, #ifdef OPTION_MASK_64BIT #if TARGET_AIX_OS @@ -24682,6 +24681,9 @@ static struct rs6000_opt_var const rs6000_opt_vars[] = { "speculate-indirect-jumps", offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps), offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), }, + { "vector-size-32", + offsetof (struct gcc_options, x_TARGET_VECTOR_SIZE_32), + offsetof (struct cl_target_option, x_TARGET_VECTOR_SIZE_32), }, }; /* Inner function to handle attribute((target("..."))) and #pragma GCC target diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 960339e19be..bb70649b7ed 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -606,7 +606,7 @@ Target Undocumented Mask(STORE_VECTOR_PAIR) Var(rs6000_isa_flags) Generate (do not generate) store vector pair instructions. mvector-size-32 -Target Undocumented Mask(VECTOR_SIZE_32) Var(rs6000_isa_flags) +Target Undocumented Var(TARGET_VECTOR_SIZE_32) Init(1) Save Generate (do not generate) vector pair instructions for vector_size(32). mrelative-jumptables