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* [gcc(refs/users/meissner/heads/work144-vsize)] Use vec_concat for building up vector pair vectors.
@ 2023-11-16 22:22 Michael Meissner
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From: Michael Meissner @ 2023-11-16 22:22 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f1a7e7b907ce863372ada1f04cc6fb75b79abd26
commit f1a7e7b907ce863372ada1f04cc6fb75b79abd26
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Nov 16 17:22:33 2023 -0500
Use vec_concat for building up vector pair vectors.
2023-11-16 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs6000.cc (rs6000_expand_vector_pair_init): Rename
gen_vpair_assemble_<mode> to gen_vpair_concat_<mode>.
* config/rs6000/vector-pair.md (UNSPEC_VPAIR_ASSEMBLE): Delete
(UNSPEC_VPAIR_SPLAT): Likewise.
(vpair_concat_<mode>): Rename from vpair_assemble_<mode>. Re-implement
it, using vec_concat.
(vpair_splat_<mode>): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 8 +++---
gcc/config/rs6000/vector-pair.md | 53 ++++++++++++++++++++++++++--------------
2 files changed, 39 insertions(+), 22 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 23276f2c92f..591948fa490 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7329,20 +7329,20 @@ rs6000_expand_vector_pair_init (rtx target, rtx vals)
bool all_same = true;
rtx first = XVECEXP (vals, 0, 0);
rtx (*gen_splat) (rtx, rtx);
- rtx (*gen_assemble) (rtx, rtx, rtx);
+ rtx (*gen_concat) (rtx, rtx, rtx);
switch (mode_vpair)
{
case E_V4DFmode:
mode_vector = V2DFmode;
gen_splat = gen_vpair_splat_v4df;
- gen_assemble = gen_vpair_assemble_v4df;
+ gen_concat = gen_vpair_concat_v4df;
break;
case E_V8SFmode:
mode_vector = V8SFmode;
gen_splat = gen_vpair_splat_v8sf;
- gen_assemble = gen_vpair_assemble_v8sf;
+ gen_concat = gen_vpair_concat_v8sf;
break;
default:
@@ -7379,7 +7379,7 @@ rs6000_expand_vector_pair_init (rtx target, rtx vals)
rs6000_expand_vector_init (vector_hi, gen_rtx_CONST_VECTOR (mode_vector, vals_hi));
rs6000_expand_vector_init (vector_lo, gen_rtx_CONST_VECTOR (mode_vector, vals_lo));
- emit_insn (gen_assemble (target, vector_hi, vector_lo));
+ emit_insn (gen_concat (target, vector_hi, vector_lo));
return;
}
diff --git a/gcc/config/rs6000/vector-pair.md b/gcc/config/rs6000/vector-pair.md
index d83bdcb209b..74253f6bbd0 100644
--- a/gcc/config/rs6000/vector-pair.md
+++ b/gcc/config/rs6000/vector-pair.md
@@ -26,10 +26,6 @@
;; interleave other instructions between these pairs of instructions if
;; possible.
-(define_c_enum "unspec"
- [UNSPEC_VPAIR_ASSEMBLE
- UNSPEC_VPAIR_SPLAT])
-
;; Iterator for all vector pair modes
(define_mode_iterator VPAIR [V8SF V4DF])
@@ -164,20 +160,41 @@
DONE;
})
-;; Assemble a vector pair from two vectors. Unlike
-;; __builtin_mma_assemble_pair, this function produces a vector pair output
-;; directly and it takes all of the vector types.
+;; Assemble a vector pair from two vectors.
;;
-;; We cannot update the two output registers atomically, so mark the output as
-;; an early clobber so we don't accidentally clobber the input operands. */
-
-(define_insn_and_split "vpair_assemble_<mode>"
- [(set (match_operand:VPAIR 0 "vsx_register_operand" "=&wa")
- (unspec:VPAIR
- [(match_operand:<VPAIR_VECTOR> 1 "mma_assemble_input_operand" "mwajeP")
- (match_operand:<VPAIR_VECTOR> 2 "mma_assemble_input_operand" "mwajeP")]
- UNSPEC_VPAIR_ASSEMBLE))]
- "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+;; We have both endian versions to change which input register will be moved
+;; the the first register in the vector pair.
+(define_expand "vpair_concat_<mode>"
+ [(set (match_operand:VPAIR 0 "vsx_register_operand")
+ (vec_concat:VPAIR
+ (match_operand:<VPAIR_VECTOR> 1 "input_operand")
+ (match_operand:<VPAIR_VECTOR> 2 "input_operand")))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32")
+
+(define_insn_and_split "vpair_concat_<mode>_be"
+ [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,&wa")
+ (vec_concat:VPAIR
+ (match_operand:<VPAIR_VECTOR> 1 "input_operand" "0,mwajeP")
+ (match_operand:<VPAIR_VECTOR> 2 "input_operand" "mwajeP,mwajeP")))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32 && WORDS_BIG_ENDIAN"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 3) (match_dup 1))
+ (set (match_dup 4) (match_dup 2))]
+{
+ machine_mode vmode = <VPAIR_VECTOR>mode;
+ rtx op0 = operands[0];
+ operands[3] = simplify_gen_subreg (vmode, op0, <MODE>mode, 0);
+ operands[4] = simplify_gen_subreg (vmode, op0, <MODE>mode, 16);
+}
+ [(set_attr "length" "8")])
+
+(define_insn_and_split "vpair_concat_<mode>_le"
+ [(set (match_operand:VPAIR 0 "vsx_register_operand" "=&wa,wa")
+ (vec_concat:VPAIR
+ (match_operand:<VPAIR_VECTOR> 1 "input_operand" "mwajeP,0")
+ (match_operand:<VPAIR_VECTOR> 2 "input_operand" "mwajeP,mwajeP")))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32 && !WORDS_BIG_ENDIAN"
"#"
"&& reload_completed"
[(set (match_dup 3) (match_dup 1))
@@ -224,7 +241,7 @@
rtx vec_elements = gen_rtx_PARALLEL (vmode, elements);
rs6000_expand_vector_init (tmp, vec_elements);
- emit_insn (gen_vpair_assemble_<mode> (op0, tmp, tmp));
+ emit_insn (gen_vpair_concat_<mode> (op0, tmp, tmp));
DONE;
})
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