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* [gcc(refs/users/meissner/heads/work144-vsize)] Add integer logical vector pair instructions
@ 2023-11-17 2:54 Michael Meissner
0 siblings, 0 replies; only message in thread
From: Michael Meissner @ 2023-11-17 2:54 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:bd8b738322b39b3c1d95d91351bdc395c7df5223
commit bd8b738322b39b3c1d95d91351bdc395c7df5223
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Nov 16 21:53:36 2023 -0500
Add integer logical vector pair instructions
2023-11-16 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/rs600-protos.h (vector_pair_to_vector_mode): Delete.
(rs6000_adjust_for_vector_pair): Delete.
* config/rs6000/rs6000.cc (rs6000_modes_tieable_p): Allow vector pair
modes to be tied with vector modes.
(vector_pair_to_vector_mode): Make static. Move higher. Add integer
vector pair support.
(rs6000_split_vpair_constan): Move higher.
(rs6000_expand_vector_pair_init): Add integer vector pair support.
(altivec_expand_vec_perm_le): Add support for permuting V32QImode.
(rs6000_adjust_for_vector_pair): Delete.
* config/rs6000/vector-pair.md (VPAIR): Add integer pair modes.
(VPAIR_FP): New mode iterator.
(VPAIR_FP_UNARY): Rename from VPAIR_UNARY.
(VPAIR_FP_BINARY): Rename from VPAIR_BINARY.
(VPAIR_LOGICAL): New mode iterator.
(VPAIR_LOGICAL_UNARY): New code iterator.
(VPAIR_LOGICAL_BINARY): Likewise.
(vpair_op): Add integer ops.
(VPAIR_VECTOR): Add integer vector pair modes.
(vpair_vector_l): Likewise.
(VPAIR_ELEMENT): Likewise.
(vpair_element_l): Likewise.
(floating point operations): Switch from VPAIR to VPAIR_FP.
(<vpair_op><mode>2, VPAIR_LOGICAL_UNARY iterator): New insns.
(<vpair_op><mode>3, VPAIR_LOGICAL_BINARY iterator): Likewise.
(nor<mode>3_1): New combiner insn.
(nor<mode>3_): Likewise.
(andc<mode>3): Likewise.
(eqv<mode>3): Likewise.
(nand<mode>3_1): Likewise.
(nand<mode>3_2): Likewise.
(*orc<mode>3): Likewise.
Diff:
---
gcc/config/rs6000/rs6000-protos.h | 2 -
gcc/config/rs6000/rs6000.cc | 206 ++++++++++-----------
gcc/config/rs6000/vector-pair.md | 364 +++++++++++++++++++++++++++++---------
3 files changed, 373 insertions(+), 199 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index b0fde773e33..13687c5b1b3 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -140,8 +140,6 @@ extern void rs6000_emit_swsqrt (rtx, rtx, bool);
extern void output_toc (FILE *, rtx, int, machine_mode);
extern void rs6000_fatal_bad_address (rtx);
extern rtx create_TOC_reference (rtx, rtx);
-extern machine_mode vector_pair_to_vector_mode (machine_mode);
-extern machine_mode rs6000_adjust_for_vector_pair (machine_mode, rtx *, int *);
extern void split_unary_vector_pair (machine_mode, rtx [], rtx (*)(rtx, rtx));
extern void split_binary_vector_pair (machine_mode, rtx [],
rtx (*)(rtx, rtx, rtx));
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 591948fa490..6f94bd204a5 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1965,14 +1965,14 @@ rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
static bool
rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
{
- if (mode1 == PTImode || mode1 == XOmode || mode2 == PTImode
- || mode2 == XOmode)
- return mode1 == mode2;
-
+ if (mode1 == PTImode || mode1 == XOmode
+ || mode2 == PTImode || mode2 == XOmode)
+ return mode1 == mode2;
+
if (VECTOR_PAIR_MODE (mode1))
return VECTOR_PAIR_MODE (mode2);
if (VECTOR_PAIR_MODE (mode2))
- return false;
+ return ALTIVEC_OR_VSX_VECTOR_MODE (mode1);
if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
@@ -7317,6 +7317,56 @@ rs6000_expand_vector_init (rtx target, rtx vals)
emit_move_insn (target, mem);
}
+/* For a vector pair mode, return the equivalent vector mode or VOIDmode. */
+
+static machine_mode
+vector_pair_to_vector_mode (machine_mode mode)
+{
+ machine_mode vmode;
+
+ switch (mode)
+ {
+ case E_V32QImode: vmode = V16QImode; break;
+ case E_V16HImode: vmode = V8HImode; break;
+ case E_V8SImode: vmode = V4SImode; break;
+ case E_V4DImode: vmode = V2DImode; break;
+ case E_V8SFmode: vmode = V4SFmode; break;
+ case E_V4DFmode: vmode = V2DFmode; break;
+ default: vmode = VOIDmode; break;
+ }
+
+ return vmode;
+}
+
+/* Split a vector constant for a type that can be held into a vector register
+ pair into 2 separate constants that can be held in a single vector register.
+ Return true if we can split the constant. */
+
+static bool
+rs6000_split_vpair_constant (rtx op, rtx *high, rtx *low)
+{
+ machine_mode vmode = vector_pair_to_vector_mode (GET_MODE (op));
+
+ *high = *low = NULL_RTX;
+
+ if (!CONST_VECTOR_P (op) || vmode == GET_MODE (op))
+ return false;
+
+ size_t nunits = GET_MODE_NUNITS (vmode);
+ rtvec hi_vec = rtvec_alloc (nunits);
+ rtvec lo_vec = rtvec_alloc (nunits);
+
+ for (size_t i = 0; i < nunits; i++)
+ {
+ RTVEC_ELT (hi_vec, i) = CONST_VECTOR_ELT (op, i);
+ RTVEC_ELT (lo_vec, i) = CONST_VECTOR_ELT (op, i + nunits);
+ }
+
+ *high = gen_rtx_CONST_VECTOR (vmode, hi_vec);
+ *low = gen_rtx_CONST_VECTOR (vmode, lo_vec);
+ return true;
+}
+
/* Initialize vector pair TARGET to VALS. */
void
@@ -7325,7 +7375,6 @@ rs6000_expand_vector_pair_init (rtx target, rtx vals)
machine_mode mode_vpair = GET_MODE (target);
machine_mode mode_vector;
size_t n_elts_vpair = GET_MODE_NUNITS (mode_vpair);
- size_t n_elts_vector = n_elts_vpair / 2;
bool all_same = true;
rtx first = XVECEXP (vals, 0, 0);
rtx (*gen_splat) (rtx, rtx);
@@ -7333,18 +7382,42 @@ rs6000_expand_vector_pair_init (rtx target, rtx vals)
switch (mode_vpair)
{
- case E_V4DFmode:
- mode_vector = V2DFmode;
- gen_splat = gen_vpair_splat_v4df;
- gen_concat = gen_vpair_concat_v4df;
+ case E_V32QImode:
+ mode_vector = V16QImode;
+ gen_splat = gen_vpair_splat_v32qi;
+ gen_concat = gen_vpair_concat_v32qi;
+ break;
+
+ case E_V16HImode:
+ mode_vector = V8HImode;
+ gen_splat = gen_vpair_splat_v16hi;
+ gen_concat = gen_vpair_concat_v16hi;
+ break;
+
+ case E_V8SImode:
+ mode_vector = V4SImode;
+ gen_splat = gen_vpair_splat_v8si;
+ gen_concat = gen_vpair_concat_v8si;
+ break;
+
+ case E_V4DImode:
+ mode_vector = V2DImode;
+ gen_splat = gen_vpair_splat_v4di;
+ gen_concat = gen_vpair_concat_v4di;
break;
case E_V8SFmode:
- mode_vector = V8SFmode;
+ mode_vector = V4SFmode;
gen_splat = gen_vpair_splat_v8sf;
gen_concat = gen_vpair_concat_v8sf;
break;
+ case E_V4DFmode:
+ mode_vector = V2DFmode;
+ gen_splat = gen_vpair_splat_v4df;
+ gen_concat = gen_vpair_concat_v4df;
+ break;
+
default:
gcc_unreachable ();
}
@@ -7368,17 +7441,13 @@ rs6000_expand_vector_pair_init (rtx target, rtx vals)
/* Break the initialization into two parts. */
rtx vector_hi = gen_reg_rtx (mode_vector);
rtx vector_lo = gen_reg_rtx (mode_vector);
- rtvec vals_hi = rtvec_alloc (n_elts_vector);
- rtvec vals_lo = rtvec_alloc (n_elts_vector);
+ rtx vals_hi;
+ rtx vals_lo;
- for (size_t i = 0; i < n_elts_vector; i++)
- {
- RTVEC_ELT (vals_hi, i) = XVECEXP (vals, 0, i);
- RTVEC_ELT (vals_lo, i) = XVECEXP (vals, 0, i + n_elts_vector);
- }
+ rs6000_split_vpair_constant (vals, &vals_hi, &vals_lo);
- rs6000_expand_vector_init (vector_hi, gen_rtx_CONST_VECTOR (mode_vector, vals_hi));
- rs6000_expand_vector_init (vector_lo, gen_rtx_CONST_VECTOR (mode_vector, vals_lo));
+ rs6000_expand_vector_init (vector_hi, vals_hi);
+ rs6000_expand_vector_init (vector_lo, vals_lo);
emit_insn (gen_concat (target, vector_hi, vector_lo));
return;
}
@@ -23526,6 +23595,7 @@ altivec_expand_vec_perm_le (rtx operands[4])
rtx tmp = target;
rtx norreg = gen_reg_rtx (V16QImode);
machine_mode mode = GET_MODE (target);
+ machine_mode qi_vmode = VECTOR_PAIR_MODE (mode) ? V32QImode : V16QImode;
/* Get everything in regs so the pattern matches. */
if (!REG_P (op0))
@@ -23533,7 +23603,7 @@ altivec_expand_vec_perm_le (rtx operands[4])
if (!REG_P (op1))
op1 = force_reg (mode, op1);
if (!REG_P (sel))
- sel = force_reg (V16QImode, sel);
+ sel = force_reg (qi_vmode, sel);
if (!REG_P (target))
tmp = gen_reg_rtx (mode);
@@ -23546,10 +23616,10 @@ altivec_expand_vec_perm_le (rtx operands[4])
{
/* Invert the selector with a VNAND if available, else a VNOR.
The VNAND is preferred for future fusion opportunities. */
- notx = gen_rtx_NOT (V16QImode, sel);
+ notx = gen_rtx_NOT (qi_vmode, sel);
iorx = (TARGET_P8_VECTOR
- ? gen_rtx_IOR (V16QImode, notx, notx)
- : gen_rtx_AND (V16QImode, notx, notx));
+ ? gen_rtx_IOR (qi_vmode, notx, notx)
+ : gen_rtx_AND (qi_vmode, notx, notx));
emit_insn (gen_rtx_SET (norreg, iorx));
/* Permute with operands reversed and adjusted selector. */
@@ -27520,94 +27590,6 @@ rs6000_split_logical (rtx operands[3],
return;
}
-/* For a vector pair mode, return the equivalent vector mode or VOIDmode. */
-
-machine_mode
-vector_pair_to_vector_mode (machine_mode mode)
-{
- machine_mode vmode;
-
- switch (mode)
- {
- case E_V8SFmode: vmode = V4SFmode; break;
- case E_V4DFmode: vmode = V2DFmode; break;
- default: vmode = VOIDmode; break;
- }
-
- return vmode;
-}
-
-/* Adjust a vector pair register, element number, and mode to reflect the
- vector register after splitting it.
-
- Return the vector mode if the mode is a vector pair, or the original mode if
- it wasn't.
-
- MODE is the original mode, P_REG is a pointer to the register to be adjust,
- and P_ELEMENT is a pointer to the element number to be adjusted. */
-
-machine_mode
-rs6000_adjust_for_vector_pair (machine_mode orig_mode,
- rtx *p_reg,
- int *p_element)
-{
- machine_mode vmode = vector_pair_to_vector_mode (orig_mode);
-
- /* Return if not a vector pair. */
- if (vmode == VOIDmode)
- return orig_mode;
-
- unsigned regno = reg_or_subregno (*p_reg);
- int element = *p_element;
-
- /* Choose which register. We have to reverse the words for little
- endian. */
- int nunits = GET_MODE_NUNITS (vmode);
- if (element >= nunits)
- {
- element -= nunits;
- if (WORDS_BIG_ENDIAN)
- regno++;
- }
- else if (!WORDS_BIG_ENDIAN)
- regno++;
-
- /* Adjust elements. */
- *p_reg = gen_rtx_REG (vmode, regno);
- *p_element = element;
- return vmode;
-}
-
-
-/* Split a vector constant for a type that can be held into a vector register
- pair into 2 separate constants that can be held in a single vector register.
- Return true if we can split the constant. */
-
-bool
-rs6000_split_vpair_constant (rtx op, rtx *high, rtx *low)
-{
- machine_mode vmode = vector_pair_to_vector_mode (GET_MODE (op));
-
- *high = *low = NULL_RTX;
-
- if (!CONST_VECTOR_P (op) || vmode == GET_MODE (op))
- return false;
-
- size_t nunits = GET_MODE_NUNITS (vmode);
- rtvec hi_vec = rtvec_alloc (nunits);
- rtvec lo_vec = rtvec_alloc (nunits);
-
- for (size_t i = 0; i < nunits; i++)
- {
- RTVEC_ELT (hi_vec, i) = CONST_VECTOR_ELT (op, i);
- RTVEC_ELT (lo_vec, i) = CONST_VECTOR_ELT (op, i + nunits);
- }
-
- *high = gen_rtx_CONST_VECTOR (vmode, hi_vec);
- *low = gen_rtx_CONST_VECTOR (vmode, lo_vec);
- return true;
-}
-
/* Split a unary vector pair insn into two separate vector insns. */
void
diff --git a/gcc/config/rs6000/vector-pair.md b/gcc/config/rs6000/vector-pair.md
index f520a232d99..60a3502169b 100644
--- a/gcc/config/rs6000/vector-pair.md
+++ b/gcc/config/rs6000/vector-pair.md
@@ -26,40 +26,73 @@
;; interleave other instructions between these pairs of instructions if
;; possible.
-;; Iterator for all vector pair modes
-(define_mode_iterator VPAIR [V8SF V4DF])
+;; Iterator for all vector pair modes. Even though we do not provide integer
+;; vector pair operations at this time, we need to support loading and storing
+;; integer vector pairs for perumte operations (and eventually compare).
+(define_mode_iterator VPAIR [V32QI V16HI V8SI V4DI V8SF V4DF])
+
+;; Floating point vector pair ops
+(define_mode_iterator VPAIR_FP [V8SF V4DF])
;; Iterator for floating point unary/binary operations.
-(define_code_iterator VPAIR_UNARY [abs neg])
-(define_code_iterator VPAIR_BINARY [plus minus mult smin smax])
+(define_code_iterator VPAIR_FP_UNARY [abs neg])
+(define_code_iterator VPAIR_FP_BINARY [plus minus mult smin smax])
+
+;; Integer vector pair ops. We need the basic logical opts to support
+;; permution on little endian systems.
+(define_mode_iterator VPAIR_LOGICAL [V32QI V16HI V8SI V4DI])
+
+;; Iterator for logical unary/binary operations.
+(define_code_iterator VPAIR_LOGICAL_UNARY [not])
+(define_code_iterator VPAIR_LOGICAL_BINARY [and ior xor])
;; Give the insn name from the opertion
(define_code_attr vpair_op [(abs "abs")
(div "div")
+ (and "and")
(fma "fma")
+ (ior "ior")
(minus "sub")
(mult "mul")
(neg "neg")
+ (not "not")
(plus "add")
(smin "smin")
- (smax "smax")])
+ (smax "smax")
+ (xor "xor")])
;; Map vector pair mode to vector mode in upper case after the vector pair is
;; split to two vectors.
-(define_mode_attr VPAIR_VECTOR [(V8SF "V4SF")
+(define_mode_attr VPAIR_VECTOR [(V32QI "V16QI")
+ (V16HI "V8HI")
+ (V8SI "V4SI")
+ (V4DI "V2DI")
+ (V8SF "V4SF")
(V4DF "V2DF")])
;; Map vector pair mode to vector mode in lower case after the vector pair is
;; split to two vectors.
-(define_mode_attr vpair_vector_l [(V8SF "v4sf")
+(define_mode_attr vpair_vector_l [(V32QI "v16qi")
+ (V16HI "v8hi")
+ (V8SI "v4si")
+ (V4DI "v2di")
+ (V8SF "v4sf")
(V4DF "v2df")])
;; Map vector pair mode to the base element mode.
-(define_mode_attr VPAIR_ELEMENT [(V8SF "SF")
+(define_mode_attr VPAIR_ELEMENT [(V32QI "QI")
+ (V16HI "HI")
+ (V8SI "SI")
+ (V4DI "DI")
+ (V8SF "SF")
(V4DF "DF")])
;; Map vector pair mode to the base element mode in lower case.
-(define_mode_attr vpair_element_l [(V8SF "sf")
+(define_mode_attr vpair_element_l [(V32QI "qi")
+ (V16HI "hi")
+ (V8SI "si")
+ (V4DI "di")
+ (V8SF "sf")
(V4DF "df")])
;; Vector pair move support.
@@ -244,13 +277,12 @@
emit_insn (gen_vpair_concat_<mode> (op0, tmp, tmp));
DONE;
})
-
\f
;; Vector pair floating point arithmetic unary operations
(define_insn_and_split "<vpair_op><mode>2"
- [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa")
- (VPAIR_UNARY:VPAIR
- (match_operand:VPAIR 1 "vsx_register_operand" "wa")))]
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa")
+ (VPAIR_FP_UNARY:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "wa")))]
"TARGET_MMA && TARGET_VECTOR_SIZE_32"
"#"
"&& reload_completed"
@@ -264,10 +296,10 @@
;; Optimize negative absolute value (both floating point and integer)
(define_insn_and_split "nabs<mode>2"
- [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa")
- (neg:VPAIR
- (abs:VPAIR
- (match_operand:VPAIR 1 "vsx_register_operand" "wa"))))]
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa")
+ (neg:VPAIR_FP
+ (abs:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "wa"))))]
"TARGET_MMA && TARGET_VECTOR_SIZE_32"
"#"
"&& reload_completed"
@@ -281,10 +313,10 @@
;; Vector pair floating point arithmetic binary operations
(define_insn_and_split "<vpair_op><mode>3"
- [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa")
- (VPAIR_BINARY:VPAIR
- (match_operand:VPAIR 1 "vsx_register_operand" "wa")
- (match_operand:VPAIR 2 "vsx_register_operand" "wa")))]
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa")
+ (VPAIR_FP_BINARY:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa")))]
"TARGET_MMA && TARGET_VECTOR_SIZE_32"
"#"
"&& reload_completed"
@@ -298,11 +330,11 @@
;; Vector pair floating point fused multiply-add
(define_insn_and_split "fma<mode>4"
- [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
- (fma:VPAIR
- (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
- (match_operand:VPAIR 2 "vsx_register_operand" "wa,0")
- (match_operand:VPAIR 3 "vsx_register_operand" "0,wa")))]
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
+ (fma:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0")
+ (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))]
"TARGET_MMA && TARGET_VECTOR_SIZE_32"
"#"
"&& reload_completed"
@@ -316,12 +348,12 @@
;; Vector pair floating point fused multiply-subtract
(define_insn_and_split "fms<mode>4"
- [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
- (fma:VPAIR
- (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
- (match_operand:VPAIR 2 "vsx_register_operand" "wa,0")
- (neg:VPAIR
- (match_operand:VPAIR 3 "vsx_register_operand" "0,wa"))))]
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
+ (fma:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0")
+ (neg:VPAIR_FP
+ (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"))))]
"TARGET_MMA && TARGET_VECTOR_SIZE_32"
"#"
"&& reload_completed"
@@ -335,12 +367,12 @@
;; Vector pair floating point negative fused multiply-add
(define_insn_and_split "nfma<mode>4"
- [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
- (neg:VPAIR
- (fma:VPAIR
- (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
- (match_operand:VPAIR 2 "vsx_register_operand" "wa,0")
- (match_operand:VPAIR 3 "vsx_register_operand" "0,wa"))))]
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
+ (neg:VPAIR_FP
+ (fma:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0")
+ (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"))))]
"TARGET_MMA && TARGET_VECTOR_SIZE_32"
"#"
"&& reload_completed"
@@ -354,13 +386,13 @@
;; Vector pair floating point fused negative multiply-subtract
(define_insn_and_split "nfms<mode>4"
- [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
- (neg:VPAIR
- (fma:VPAIR
- (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
- (match_operand:VPAIR 2 "vsx_register_operand" "wa,0")
- (neg:VPAIR
- (match_operand:VPAIR 3 "vsx_register_operand" "0,wa")))))]
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
+ (neg:VPAIR_FP
+ (fma:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0")
+ (neg:VPAIR_FP
+ (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))))]
"TARGET_MMA && TARGET_VECTOR_SIZE_32"
"#"
"&& reload_completed"
@@ -374,84 +406,246 @@
;; Optimize vector pair (a * b) + c into fma (a, b, c)
(define_insn_and_split "*fma_fpcontract_<mode>4"
- [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
- (plus:VPAIR
- (mult:VPAIR
- (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
- (match_operand:VPAIR 2 "vsx_register_operand" "wa,0"))
- (match_operand:VPAIR 3 "vsx_register_operand" "0,wa")))]
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
+ (plus:VPAIR_FP
+ (mult:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
+ (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))]
"TARGET_MMA && TARGET_VECTOR_SIZE_32
&& flag_fp_contract_mode == FP_CONTRACT_FAST"
"#"
"&& 1"
[(set (match_dup 0)
- (fma:VPAIR (match_dup 1)
- (match_dup 2)
- (match_dup 3)))]
+ (fma:VPAIR_FP (match_dup 1)
+ (match_dup 2)
+ (match_dup 3)))]
{
}
[(set_attr "length" "8")])
;; Optimize vector pair (a * b) - c into fma (a, b, -c)
(define_insn_and_split "*fms_fpcontract_<mode>4"
- [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
- (minus:VPAIR
- (mult:VPAIR
- (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
- (match_operand:VPAIR 2 "vsx_register_operand" "wa,0"))
- (match_operand:VPAIR 3 "vsx_register_operand" "0,wa")))]
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
+ (minus:VPAIR_FP
+ (mult:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
+ (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))]
"TARGET_MMA && TARGET_VECTOR_SIZE_32
&& flag_fp_contract_mode == FP_CONTRACT_FAST"
"#"
"&& 1"
[(set (match_dup 0)
- (fma:VPAIR (match_dup 1)
- (match_dup 2)
- (neg:VPAIR (match_dup 3))))]
+ (fma:VPAIR_FP (match_dup 1)
+ (match_dup 2)
+ (neg:VPAIR_FP
+ (match_dup 3))))]
{
}
[(set_attr "length" "8")])
;; Optimize vector pair -((a * b) + c) into -fma (a, b, c)
(define_insn_and_split "*nfma_fpcontract_<mode>4"
- [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
- (neg:VPAIR
- (plus:VPAIR
- (mult:VPAIR
- (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
- (match_operand:VPAIR 2 "vsx_register_operand" "wa,0"))
- (match_operand:VPAIR 3 "vsx_register_operand" "0,wa"))))]
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
+ (neg:VPAIR_FP
+ (plus:VPAIR_FP
+ (mult:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
+ (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"))))]
"TARGET_MMA && TARGET_VECTOR_SIZE_32
&& flag_fp_contract_mode == FP_CONTRACT_FAST"
"#"
"&& 1"
[(set (match_dup 0)
- (neg:VPAIR
- (fma:VPAIR (match_dup 1)
- (match_dup 2)
- (match_dup 3))))]
+ (neg:VPAIR_FP
+ (fma:VPAIR_FP (match_dup 1)
+ (match_dup 2)
+ (match_dup 3))))]
{
}
[(set_attr "length" "8")])
;; Optimize vector pair -((a * b) - c) into -fma (a, b, -c)
(define_insn_and_split "*nfms_fpcontract_<mode>4"
- [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
- (neg:VPAIR
- (minus:VPAIR
- (mult:VPAIR
- (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
- (match_operand:VPAIR 2 "vsx_register_operand" "wa,0"))
- (match_operand:VPAIR 3 "vsx_register_operand" "0,wa"))))]
+ [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
+ (neg:VPAIR_FP
+ (minus:VPAIR_FP
+ (mult:VPAIR_FP
+ (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
+ (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
+ (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"))))]
"TARGET_MMA && TARGET_VECTOR_SIZE_32
&& flag_fp_contract_mode == FP_CONTRACT_FAST"
"#"
"&& 1"
[(set (match_dup 0)
- (neg:VPAIR
- (fma:VPAIR (match_dup 1)
- (match_dup 2)
- (neg:VPAIR (match_dup 3)))))]
+ (neg:VPAIR_FP
+ (fma:VPAIR_FP (match_dup 1)
+ (match_dup 2)
+ (neg:VPAIR_FP
+ (match_dup 3)))))]
+{
+}
+ [(set_attr "length" "8")])
+\f
+;; Vector pair integer unary operations
+(define_insn_and_split "<vpair_op><mode>2"
+ [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
+ (VPAIR_FP_UNARY:VPAIR_LOGICAL
+ (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa")))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ split_unary_vector_pair (<VPAIR_VECTOR>mode, operands,
+ gen_<vpair_op><vpair_vector_l>2);
+ DONE;
+}
+ [(set_attr "length" "8")])
+
+;; Vector pair logical binary operations
+(define_insn_and_split "<vpair_op><mode>3"
+ [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
+ (VPAIR_FP_BINARY:VPAIR_LOGICAL
+ (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa")
+ (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa")))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
+ gen_<vpair_op><vpair_vector_l>3);
+ DONE;
+}
+ [(set_attr "length" "8")])
+
+;; Optiomize vector pair ~(a | b) or ((~a) & (~b)) to produce xxlnor
+(define_insn_and_split "*nor<mode>3_1"
+ [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
+ (not:VPAIR_LOGICAL
+ (ior:VPAIR_LOGICAL
+ (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa")
+ (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa"))))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
+ gen_nor<vpair_vector_l>3);
+ DONE;
+}
+ [(set_attr "length" "8")])
+
+(define_insn_and_split "*nor<mode>3_2"
+ [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
+ (and:VPAIR_LOGICAL
+ (not:VPAIR_LOGICAL
+ (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa"))
+ (not:VPAIR_LOGICAL
+ (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa"))))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
+ gen_nor<vpair_vector_l>3);
+ DONE;
+}
+ [(set_attr "length" "8")])
+
+;; Optimize vector pair (~a) & b to use xxlandc
+(define_insn_and_split "*andc<mode>3"
+ [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
+ (and:VPAIR_LOGICAL
+ (not:VPAIR_LOGICAL
+ (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa"))
+ (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa")))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
{
+ split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
+ gen_andc<vpair_vector_l>3);
+ DONE;
+}
+ [(set_attr "length" "8")])
+
+;; Optimize vector pair ~(a ^ b) to produce xxleqv
+(define_insn_and_split "*eqv<mode>3"
+ [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
+ (not:VPAIR_LOGICAL
+ (xor:VPAIR_LOGICAL
+ (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa")
+ (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa"))))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
+ gen_nor<vpair_vector_l>3);
+ DONE;
+}
+[(set_attr "length" "8")])
+
+
+;; Optiomize vector pair ~(a & b) or ((~a) | (~b)) to produce xxlnand
+(define_insn_and_split "*nand<mode>3_1"
+ [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
+ (not:VPAIR_LOGICAL
+ (and:VPAIR_LOGICAL
+ (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa")
+ (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa"))))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
+ gen_nand<vpair_vector_l>3);
+ DONE;
+}
+ [(set_attr "length" "8")])
+
+(define_insn_and_split "*nand<mode>3_2"
+ [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
+ (ior:VPAIR_LOGICAL
+ (not:VPAIR_LOGICAL
+ (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa"))
+ (not:VPAIR_LOGICAL
+ (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa"))))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
+ gen_nand<vpair_vector_l>3);
+ DONE;
+}
+ [(set_attr "length" "8")])
+
+;; Optimize vector pair (~a) | b to produce xxlorc
+(define_insn_and_split "*orc<mode>3"
+ [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
+ (ior:VPAIR_LOGICAL
+ (not:VPAIR_LOGICAL
+ (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa"))
+ (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa")))]
+ "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
+ gen_orc<vpair_vector_l>3);
+ DONE;
}
[(set_attr "length" "8")])
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2023-11-17 2:54 [gcc(refs/users/meissner/heads/work144-vsize)] Add integer logical vector pair instructions Michael Meissner
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