public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc(refs/users/meissner/heads/work144-vsubreg)] Sync vsize patches 401 - 404.
@ 2023-11-17  3:52 Michael Meissner
  0 siblings, 0 replies; only message in thread
From: Michael Meissner @ 2023-11-17  3:52 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:99e1c0d1e1e62ebbe8c59663ec653305eb34d5c1

commit 99e1c0d1e1e62ebbe8c59663ec653305eb34d5c1
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Nov 16 22:52:37 2023 -0500

    Sync vsize patches 401 - 404.
    
    2023-11-09  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000.cc: Sync changes with vsize branch, patches 401 -
            404.
            * config/rs6000/rs6000.md: Likewise.
            * config/rs6000/vector-pair.md: Likewise.
            * config/rs6000/vector.md: Likewise.
            * config/rs6000/vsx.md: Likewise.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vector-size-32-3.c: Delete.
            * gcc.target/powerpc/vector-size-32-4.c: Delete.
            * gcc.target/powerpc/vector-size-32-5.c: Delete.
            * gcc.target/powerpc/vector-size-32-6.c: Delete.

Diff:
---
 gcc/config/rs6000/rs6000.cc                        |  76 +---
 gcc/config/rs6000/rs6000.md                        |   3 +-
 gcc/config/rs6000/vector-pair.md                   | 450 +++++----------------
 gcc/config/rs6000/vector.md                        |  17 +-
 gcc/config/rs6000/vsx.md                           |  78 +---
 .../gcc.target/powerpc/vector-size-32-3.c          | 137 -------
 .../gcc.target/powerpc/vector-size-32-4.c          | 137 -------
 .../gcc.target/powerpc/vector-size-32-5.c          | 137 -------
 .../gcc.target/powerpc/vector-size-32-6.c          | 137 -------
 9 files changed, 130 insertions(+), 1042 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index e6b27c69063..cc8a98bd0ee 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -2949,22 +2949,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
 
   if (TARGET_MMA && TARGET_VECTOR_SIZE_32)
     {
-      rs6000_vector_unit[V32QImode] = VECTOR_NONE;
-      rs6000_vector_mem[V32QImode] = VECTOR_VSX;
-      rs6000_vector_align[V32QImode] = 256;
-
-      rs6000_vector_unit[V16HImode] = VECTOR_NONE;
-      rs6000_vector_mem[V16HImode] = VECTOR_VSX;
-      rs6000_vector_align[V16HImode] = 256;
-
-      rs6000_vector_unit[V8SImode] = VECTOR_NONE;
-      rs6000_vector_mem[V8SImode] = VECTOR_VSX;
-      rs6000_vector_align[V8SImode] = 256;
-
-      rs6000_vector_unit[V4DImode] = VECTOR_NONE;
-      rs6000_vector_mem[V4DImode] = VECTOR_VSX;
-      rs6000_vector_align[V4DImode] = 256;
-
       rs6000_vector_unit[V8SFmode] = VECTOR_NONE;
       rs6000_vector_mem[V8SFmode] = VECTOR_VSX;
       rs6000_vector_align[V8SFmode] = 256;
@@ -3108,14 +3092,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
 
 	      if (TARGET_MMA && TARGET_VECTOR_SIZE_32)
 		{
-		  reg_addr[V32QImode].reload_store = CODE_FOR_reload_v32qi_di_store;
-		  reg_addr[V32QImode].reload_load = CODE_FOR_reload_v32qi_di_load;
-		  reg_addr[V16HImode].reload_store = CODE_FOR_reload_v16hi_di_store;
-		  reg_addr[V16HImode].reload_load = CODE_FOR_reload_v16hi_di_load;
-		  reg_addr[V8SImode].reload_store = CODE_FOR_reload_v8si_di_store;
-		  reg_addr[V8SImode].reload_load = CODE_FOR_reload_v8si_di_load;
-		  reg_addr[V4DImode].reload_store = CODE_FOR_reload_v4di_di_store;
-		  reg_addr[V4DImode].reload_load = CODE_FOR_reload_v4di_di_load;
 		  reg_addr[V8SFmode].reload_store = CODE_FOR_reload_v8sf_di_store;
 		  reg_addr[V8SFmode].reload_load = CODE_FOR_reload_v8sf_di_load;
 		  reg_addr[V4DFmode].reload_store = CODE_FOR_reload_v4df_di_store;
@@ -3181,14 +3157,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
 
 	  if (TARGET_MMA && TARGET_VECTOR_SIZE_32)
 	    {
-	      reg_addr[V32QImode].reload_store = CODE_FOR_reload_v32qi_si_store;
-	      reg_addr[V32QImode].reload_load = CODE_FOR_reload_v32qi_si_load;
-	      reg_addr[V16HImode].reload_store = CODE_FOR_reload_v16hi_si_store;
-	      reg_addr[V16HImode].reload_load = CODE_FOR_reload_v16hi_si_load;
-	      reg_addr[V8SImode].reload_store = CODE_FOR_reload_v8si_si_store;
-	      reg_addr[V8SImode].reload_load = CODE_FOR_reload_v8si_si_load;
-	      reg_addr[V4DImode].reload_store = CODE_FOR_reload_v4di_si_store;
-	      reg_addr[V4DImode].reload_load = CODE_FOR_reload_v4di_si_load;
 	      reg_addr[V8SFmode].reload_store = CODE_FOR_reload_v8sf_si_store;
 	      reg_addr[V8SFmode].reload_load = CODE_FOR_reload_v8sf_si_load;
 	      reg_addr[V4DFmode].reload_store = CODE_FOR_reload_v4df_si_store;
@@ -7727,43 +7695,15 @@ rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
 	      return;
 	    }
 	  break;
-	case E_V4DImode:
-	  if (TARGET_MMA && TARGET_VECTOR_SIZE_32)
-	    {
-	      emit_insn (gen_vsx_extract_v4di (target, vec, elt));
-	      return;
-	    }
-	  break;
-	case E_V8SImode:
-	  if (TARGET_MMA && TARGET_VECTOR_SIZE_32)
-	    {
-	      emit_insn (gen_vsx_extract_v8si (target, vec, elt));
-	      return;
-	    }
-	  break;
-	case E_V16HImode:
-	  if (TARGET_MMA && TARGET_VECTOR_SIZE_32)
-	    {
-	      emit_insn (gen_vsx_extract_v16hi (target, vec, elt));
-	      return;
-	    }
-	  break;
-	case E_V32QImode:
-	  if (TARGET_MMA && TARGET_VECTOR_SIZE_32)
-	    {
-	      emit_insn (gen_vsx_extract_v32qi (target, vec, elt));
-	      return;
-	    }
-	  break;
 	case E_V4DFmode:
-	  if (TARGET_MMA)
+	  if (TARGET_MMA && TARGET_VECTOR_SIZE_32)
 	    {
 	      emit_insn (gen_vsx_extract_v4df (target, vec, elt));
 	      return;
 	    }
 	  break;
 	case E_V8SFmode:
-	  if (TARGET_MMA)
+	  if (TARGET_MMA && TARGET_VECTOR_SIZE_32)
 	    {
 	      emit_insn (gen_vsx_extract_v8sf (target, vec, elt));
 	      return;
@@ -8812,10 +8752,6 @@ reg_offset_addressing_ok_p (machine_mode mode)
     case E_OOmode:
     case E_V8SFmode:
     case E_V4DFmode:
-    case E_V32QImode:
-    case E_V16HImode:
-    case E_V8SImode:
-    case E_V4DImode:
     case E_XOmode:
       return TARGET_MMA;
 
@@ -11317,17 +11253,13 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
 	operands[1] = force_const_mem (mode, operands[1]);
       break;
 
-    case E_V32QImode:
     case E_V16QImode:
-    case E_V16HImode:
     case E_V8HImode:
     case E_V8SFmode:
     case E_V4SFmode:
-    case E_V8SImode:
     case E_V4SImode:
     case E_V4DFmode:
     case E_V2DFmode:
-    case E_V4DImode:
     case E_V2DImode:
     case E_V1TImode:
       if (CONSTANT_P (operands[1])
@@ -27534,11 +27466,7 @@ vector_pair_to_vector_mode (machine_mode mode)
 
   switch (mode)
     {
-    case E_V32QImode: vmode = V16QImode; break;
-    case E_V16HImode: vmode = V8HImode;  break;
-    case E_V8SImode:  vmode = V4SImode;  break;
     case E_V8SFmode:  vmode = V4SFmode;  break;
-    case E_V4DImode:  vmode = V2DImode;  break;
     case E_V4DFmode:  vmode = V2DFmode;  break;
     default:          vmode = VOIDmode;  break;
     }
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9feb3e5b3e1..0c46f16f68c 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -815,9 +815,8 @@
 ;; Reload iterator for creating the function to allocate a base register to
 ;; supplement addressing modes.
 (define_mode_iterator RELOAD [V16QI V8HI V4SI V2DI V4SF V2DF V1TI
-			      V32QI V16HI V8SI V4DI V8SF V4DF
 			      SF SD SI DF DD DI TI PTI KF IF TF
-			      OO XO])
+			      OO XO V8SF V4DF])
 
 ;; Iterate over smin, smax
 (define_code_iterator fp_minmax	[smin smax])
diff --git a/gcc/config/rs6000/vector-pair.md b/gcc/config/rs6000/vector-pair.md
index 839330a6462..c354b54242a 100644
--- a/gcc/config/rs6000/vector-pair.md
+++ b/gcc/config/rs6000/vector-pair.md
@@ -883,43 +883,32 @@
 \f
 ;; Support for 256-bit vector modes.
 ;; Iterator for all vector pair modes
-(define_mode_iterator VPAIR [V32QI V16HI V8SI V4DI V8SF V4DF])
+(define_mode_iterator VPAIR [V8SF V4DF])
 
-;; Iterator for the integer vector pair modes
-(define_mode_iterator VPAIR_INT [V32QI V16HI V8SI V4DI])
-
-;; Special iterators for NEG (V4SI and V2DI have vneg{w,d}), while V16QI and
-;; V8HI have to use a subtract from 0.
-(define_mode_iterator VPAIR_NEG_VNEG [V4DI V8SI])
-(define_mode_iterator VPAIR_NEG_SUB [V32QI V16HI])
-
-;; Iterator for the floating point vector pair modes
-(define_mode_iterator VPAIR_FP [V8SF V4DF])
-
-;; Iterator doing unary/binary arithmetic on vector pairs.  Split it into
-;; integer and floating point operations.
-(define_code_iterator VPAIR_INT_UNARY   [not])
-(define_code_iterator VPAIR_INT_BINARY  [plus minus smin smax])
-(define_code_iterator VPAIR_INT_LOGICAL [and ior xor])
-
-(define_code_iterator VPAIR_FP_UNARY  [abs neg])
-(define_code_iterator VPAIR_FP_BINARY [plus minus mult smin smax])
+;; Iterator for floating point unary/binary operations.
+(define_code_iterator VPAIR_UNARY  [abs neg])
+(define_code_iterator VPAIR_BINARY [plus minus mult smin smax])
 
 ;; Give the insn name from the opertion
-(define_code_attr vpair_op [(abs      "abs")
-			    (and      "and")
-			    (fma      "fma")
-			    (ior      "ior")
-			    (minus    "sub")
-			    (mult     "mul")
-			    (not      "one_cmpl")
-			    (neg      "neg")
-			    (plus     "add")
-			    (smin     "smin")
-			    (smax     "smax")
-			    (umin     "umin")
-			    (umax     "umax")
-			    (xor      "xor")])
+(define_code_attr vpair_op [(abs   "abs")
+			    (div   "div")
+			    (fma   "fma")
+			    (minus "sub")
+			    (mult  "mul")
+			    (neg   "neg")
+			    (plus  "add")
+			    (smin  "smin")
+			    (smax  "smax")])
+
+;; Map vector pair mode to vector mode in upper case after the vector pair is
+;; split to two vectors.
+(define_mode_attr VPAIR_VECTOR [(V8SF  "V4SF")
+                                (V4DF  "V2DF")])
+
+;; Map vector pair mode to vector mode in lower case after the vector pair is
+;; split to two vectors.
+(define_mode_attr vpair_vector [(V8SF  "v4sf")
+				(V4DF  "v2df")])
 
 ;; Vector pair move support.
 (define_expand "mov<mode>"
@@ -934,7 +923,7 @@
 (define_insn_and_split "*mov<mode>"
   [(set (match_operand:VPAIR 0 "nonimmediate_operand" "=wa,wa,ZwO,QwO,wa")
 	(match_operand:VPAIR 1 "input_operand" "ZwO,QwO,wa,wa,wa"))]
-  "TARGET_MMA
+  "TARGET_MMA && TARGET_VECTOR_SIZE_32
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
   "@
@@ -960,9 +949,9 @@
 \f
 ;; Vector pair floating point arithmetic unary operations
 (define_insn_and_split "<vpair_op><mode>2"
-  [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa")
-	(VPAIR_FP_UNARY:VPAIR_FP
-	 (match_operand:VPAIR_FP 1 "vsx_register_operand" "wa")))]
+  [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa")
+	(VPAIR_UNARY:VPAIR
+	 (match_operand:VPAIR 1 "vsx_register_operand" "wa")))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -976,10 +965,10 @@
 
 ;; Optimize negative absolute value (both floating point and integer)
 (define_insn_and_split "nabs<mode>2"
-  [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa")
-	(neg:VPAIR_FP
-	 (abs:VPAIR_FP
-	  (match_operand:VPAIR_FP 1 "vsx_register_operand" "wa"))))]
+  [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa")
+	(neg:VPAIR
+	 (abs:VPAIR
+	  (match_operand:VPAIR 1 "vsx_register_operand" "wa"))))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -993,10 +982,10 @@
 
 ;; Vector pair floating point arithmetic binary operations
 (define_insn_and_split "<vpair_op><mode>3"
-  [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa")
-	(VPAIR_FP_BINARY:VPAIR_FP
-	 (match_operand:VPAIR_FP 1 "vsx_register_operand" "wa")
-	 (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa")))]
+  [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa")
+	(VPAIR_BINARY:VPAIR
+	 (match_operand:VPAIR 1 "vsx_register_operand" "wa")
+	 (match_operand:VPAIR 2 "vsx_register_operand" "wa")))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -1009,12 +998,12 @@
   [(set_attr "length" "8")])
 
 ;; Vector pair floating point fused multiply-add
-(define_insn_and_split "fma<mode>3"
-  [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
-	(fma:VPAIR_FP
-	 (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
-	 (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0")
-	 (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))]
+(define_insn_and_split "fma<mode>4"
+  [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
+	(fma:VPAIR
+	 (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
+	 (match_operand:VPAIR 2 "vsx_register_operand" "wa,0")
+	 (match_operand:VPAIR 3 "vsx_register_operand" "0,wa")))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -1027,13 +1016,13 @@
   [(set_attr "length" "8")])
 
 ;; Vector pair floating point fused multiply-subtract
-(define_insn_and_split "fms<mode>3"
-  [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
-	(fma:VPAIR_FP
-	 (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
-	 (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0")
-	 (neg:VPAIR_FP
-	  (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"))))]
+(define_insn_and_split "fms<mode>4"
+  [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
+	(fma:VPAIR
+	 (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
+	 (match_operand:VPAIR 2 "vsx_register_operand" "wa,0")
+	 (neg:VPAIR
+	  (match_operand:VPAIR 3 "vsx_register_operand" "0,wa"))))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -1046,13 +1035,13 @@
   [(set_attr "length" "8")])
 
 ;; Vector pair floating point negative fused multiply-add
-(define_insn_and_split "nfma<mode>3"
-  [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
-	(neg:VPAIR_FP
-	 (fma:VPAIR_FP
-	  (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
-	  (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0")
-	  (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"))))]
+(define_insn_and_split "nfma<mode>4"
+  [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
+	(neg:VPAIR
+	 (fma:VPAIR
+	  (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
+	  (match_operand:VPAIR 2 "vsx_register_operand" "wa,0")
+	  (match_operand:VPAIR 3 "vsx_register_operand" "0,wa"))))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -1065,14 +1054,14 @@
   [(set_attr "length" "8")])
 
 ;; Vector pair floating point fused negative multiply-subtract
-(define_insn_and_split "nfms<mode>3"
-  [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
-	(neg:VPAIR_FP
-	 (fma:VPAIR_FP
-	  (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
-	  (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0")
-	  (neg:VPAIR_FP
-	   (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))))]
+(define_insn_and_split "nfms<mode>4"
+  [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
+	(neg:VPAIR
+	 (fma:VPAIR
+	  (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
+	  (match_operand:VPAIR 2 "vsx_register_operand" "wa,0")
+	  (neg:VPAIR
+	   (match_operand:VPAIR 3 "vsx_register_operand" "0,wa")))))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -1085,310 +1074,85 @@
   [(set_attr "length" "8")])
 
 ;; Optimize vector pair (a * b) + c into fma (a, b, c)
-(define_insn_and_split "*fma_fpcontract_<mode>3"
-  [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
-	(plus:VPAIR_FP
-	 (mult:VPAIR_FP
-	  (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
-	  (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
-	 (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))]
+(define_insn_and_split "*fma_fpcontract_<mode>4"
+  [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
+	(plus:VPAIR
+	 (mult:VPAIR
+	  (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
+	  (match_operand:VPAIR 2 "vsx_register_operand" "wa,0"))
+	 (match_operand:VPAIR 3 "vsx_register_operand" "0,wa")))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32
    && flag_fp_contract_mode == FP_CONTRACT_FAST"
   "#"
   "&& 1"
   [(set (match_dup 0)
-	(fma:VPAIR_FP (match_dup 1)
-		      (match_dup 2)
-		      (match_dup 3)))]
+	(fma:VPAIR (match_dup 1)
+		   (match_dup 2)
+		   (match_dup 3)))]
 {
 }
   [(set_attr "length" "8")])
 
 ;; Optimize vector pair (a * b) - c into fma (a, b, -c)
-(define_insn_and_split "*fms_fpcontract_<mode>3"
-  [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
-	(minus:VPAIR_FP
-	 (mult:VPAIR_FP
-	  (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
-	  (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
-	 (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa")))]
+(define_insn_and_split "*fms_fpcontract_<mode>4"
+  [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
+	(minus:VPAIR
+	 (mult:VPAIR
+	  (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
+	  (match_operand:VPAIR 2 "vsx_register_operand" "wa,0"))
+	 (match_operand:VPAIR 3 "vsx_register_operand" "0,wa")))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32
    && flag_fp_contract_mode == FP_CONTRACT_FAST"
   "#"
   "&& 1"
   [(set (match_dup 0)
-	(fma:VPAIR_FP (match_dup 1)
-		      (match_dup 2)
-		      (neg:VPAIR_FP
-		       (match_dup 3))))]
+	(fma:VPAIR (match_dup 1)
+		   (match_dup 2)
+		   (neg:VPAIR (match_dup 3))))]
 {
 }
   [(set_attr "length" "8")])
 
 ;; Optimize vector pair -((a * b) + c) into -fma (a, b, c)
-(define_insn_and_split "*nfma_fpcontract_<mode>3"
-  [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
-	(neg:VPAIR_FP
-	 (plus:VPAIR_FP
-	  (mult:VPAIR_FP
-	   (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
-	   (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
-	  (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"))))]
+(define_insn_and_split "*nfma_fpcontract_<mode>4"
+  [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
+	(neg:VPAIR
+	 (plus:VPAIR
+	  (mult:VPAIR
+	   (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
+	   (match_operand:VPAIR 2 "vsx_register_operand" "wa,0"))
+	  (match_operand:VPAIR 3 "vsx_register_operand" "0,wa"))))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32
    && flag_fp_contract_mode == FP_CONTRACT_FAST"
   "#"
   "&& 1"
   [(set (match_dup 0)
-	(neg:VPAIR_FP
-	 (fma:VPAIR_FP (match_dup 1)
-		       (match_dup 2)
-		       (match_dup 3))))]
+	(neg:VPAIR
+	 (fma:VPAIR (match_dup 1)
+		    (match_dup 2)
+		    (match_dup 3))))]
 {
 }
   [(set_attr "length" "8")])
 
 ;; Optimize vector pair -((a * b) - c) into -fma (a, b, -c)
-(define_insn_and_split "*nfms_fpcontract_<mode>3"
-  [(set (match_operand:VPAIR_FP 0 "vsx_register_operand" "=wa,wa")
-	(neg:VPAIR_FP
-	 (minus:VPAIR_FP
-	  (mult:VPAIR_FP
-	   (match_operand:VPAIR_FP 1 "vsx_register_operand" "%wa,wa")
-	   (match_operand:VPAIR_FP 2 "vsx_register_operand" "wa,0"))
-	  (match_operand:VPAIR_FP 3 "vsx_register_operand" "0,wa"))))]
+(define_insn_and_split "*nfms_fpcontract_<mode>4"
+  [(set (match_operand:VPAIR 0 "vsx_register_operand" "=wa,wa")
+	(neg:VPAIR
+	 (minus:VPAIR
+	  (mult:VPAIR
+	   (match_operand:VPAIR 1 "vsx_register_operand" "%wa,wa")
+	   (match_operand:VPAIR 2 "vsx_register_operand" "wa,0"))
+	  (match_operand:VPAIR 3 "vsx_register_operand" "0,wa"))))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32
    && flag_fp_contract_mode == FP_CONTRACT_FAST"
   "#"
   "&& 1"
   [(set (match_dup 0)
-	(neg:VPAIR_FP
-	 (fma:VPAIR_FP (match_dup 1)
-		       (match_dup 2)
-		       (neg:VPAIR_FP
-			(match_dup 3)))))]
-{
-}
-  [(set_attr "length" "8")])
-
-\f
-;; Vector pair integer arithmetic unary operations
-(define_insn_and_split "<vpair_op><mode>2"
-  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
-	(VPAIR_INT_UNARY:VPAIR_INT
-	 (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")))]
-  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-{
-  split_unary_vector_pair (<VPAIR_VECTOR>mode, operands,
-			   gen_<vpair_op><vpair_vector>2);
-  DONE;
-}
-  [(set_attr "length" "8")])
-
-;; Vector pair negate if we have the VNEGx instruction.
-(define_insn_and_split "neg<mode>2"
-  [(set (match_operand:VPAIR_NEG_VNEG 0 "vsx_register_operand" "=v")
-	(neg:VPAIR_NEG_VNEG
-	 (match_operand:VPAIR_NEG_VNEG 1 "vsx_register_operand" "v")))]
-  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-{
-  split_unary_vector_pair (<VPAIR_VECTOR>mode, operands,
-			   gen_neg<vpair_vector>2);
-  DONE;
-}
-  [(set_attr "length" "8")])
-
-;; Vector pair negate if we have to do a subtract from 0
-(define_insn_and_split "neg<mode>2"
-  [(set (match_operand:VPAIR_NEG_SUB 0 "vsx_register_operand" "=v")
-	(neg:VPAIR_NEG_SUB
-	 (match_operand:VPAIR_NEG_SUB 1 "vsx_register_operand" "v")))
-   (clobber (match_scratch:<VPAIR_VECTOR> 2 "=&v"))]
-  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-{
-  enum machine_mode mode = <VPAIR_VECTOR>mode;
-  rtx tmp = operands[2];
-  unsigned reg0 = reg_or_subregno (operands[0]);
-  unsigned reg1 = reg_or_subregno (operands[1]);
-
-  emit_move_insn (tmp, CONST0_RTX (mode));
-  emit_insn (gen_sub<vpair_vector>3 (gen_rtx_REG (mode, reg0),
-				     tmp,
-				     gen_rtx_REG (mode, reg1)));
-
-  emit_insn (gen_sub<vpair_vector>3 (gen_rtx_REG (mode, reg0 + 1),
-				     tmp,
-				     gen_rtx_REG (mode, reg1 + 1)));
-
-  DONE;
-}
-  [(set_attr "length" "8")])
-
-;; Vector pair integer arithmetic binary operations
-(define_insn_and_split "<vpair_op><mode>3"
-  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=v")
-	(VPAIR_INT_BINARY:VPAIR_INT
-	 (match_operand:VPAIR_INT 1 "vsx_register_operand" "v")
-	 (match_operand:VPAIR_INT 2 "vsx_register_operand" "v")))]
-  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-{
-  split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
-			    gen_<vpair_op><vpair_vector>3);
-  DONE;
-}
-  [(set_attr "length" "8")])
-
-;; Vector pair integer arithmetic logical operations
-(define_insn_and_split "<vpair_op><mode>3"
-  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
-	(VPAIR_INT_LOGICAL:VPAIR_INT
-	 (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")
-	 (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa")))]
-  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-{
-  split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
-			    gen_<vpair_op><vpair_vector>3);
-  DONE;
-}
-  [(set_attr "length" "8")])
-
-;; Optiomize vector pair ~(a | b)  or ((~a) & (~b)) to produce xxlnor
-(define_insn_and_split "*nor<mode>3_1"
-  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
-	(not:VPAIR_INT
-	 (ior:VPAIR_INT
-	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")
-	  (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))]
-  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-{
-  split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
-			    gen_nor<vpair_vector>3);
-  DONE;
-}
-  [(set_attr "length" "8")])
-
-(define_insn_and_split "*nor<mode>3_2"
-  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
-	(and:VPAIR_INT
-	 (not:VPAIR_INT
-	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa"))
-	 (not:VPAIR_INT
-	  (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))]
-  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-{
-  split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
-			    gen_nor<vpair_vector>3);
-  DONE;
-}
-  [(set_attr "length" "8")])
-
-;; Optimize vector pair (~a) & b to use xxlandc
-(define_insn_and_split "*andc<mode>3"
-  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
-	(and:VPAIR_INT
-	 (not:VPAIR_INT
-	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa"))
-	 (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa")))]
-  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-{
-  split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
-			    gen_andc<vpair_vector>3);
-  DONE;
-}
-  [(set_attr "length" "8")])
-
-;; Optimize vector pair ~(a ^ b) to produce xxleqv
-(define_insn_and_split "*eqv<mode>3"
-  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
-	(not:VPAIR_INT
-	 (xor:VPAIR_INT
-	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")
-	  (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))]
-  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-{
-  split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
-			    gen_nor<vpair_vector>3);
-  DONE;
-}
-[(set_attr "length" "8")])
-
-
-;; Optiomize vector pair ~(a & b) or ((~a) | (~b)) to produce xxlnand
-(define_insn_and_split "*nand<mode>3_1"
-  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
-	(not:VPAIR_INT
-	 (and:VPAIR_INT
-	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")
-	  (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))]
-  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-{
-  split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
-			    gen_nand<vpair_vector>3);
-  DONE;
-}
-  [(set_attr "length" "8")])
-
-(define_insn_and_split "*nand<mode>3_2"
-  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
-	(ior:VPAIR_INT
-	 (not:VPAIR_INT
-	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa"))
-	 (not:VPAIR_INT
-	  (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))]
-  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
+	(neg:VPAIR
+	 (fma:VPAIR (match_dup 1)
+		    (match_dup 2)
+		    (neg:VPAIR (match_dup 3)))))]
 {
-  split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
-			    gen_nand<vpair_vector>3);
-  DONE;
-}
-  [(set_attr "length" "8")])
-
-;; Optimize vector pair (~a) | b to produce xxlorc
-(define_insn_and_split "*orc<mode>3"
-  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
-	(ior:VPAIR_INT
-	 (not:VPAIR_INT
-	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa"))
-	 (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa")))]
-  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
-  "#"
-  "&& reload_completed"
-  [(const_int 0)]
-{
-  split_binary_vector_pair (<VPAIR_VECTOR>mode, operands,
-			    gen_orc<vpair_vector>3);
-  DONE;
 }
   [(set_attr "length" "8")])
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 3d713f6b7f8..94b5349eac7 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -62,7 +62,14 @@
 (define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF V1TI])
 
 ;; Vector init/extract modes
-(define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
+(define_mode_iterator VEC_E [V16QI
+			     V8HI
+			     V4SI
+			     V2DI
+			     V4SF
+			     V2DF
+			     (V8SF	"TARGET_MMA && TARGET_VECTOR_SIZE_32")
+			     (V4DF	"TARGET_MMA && TARGET_VECTOR_SIZE_32")])
 
 ;; Vector modes for 64-bit base types
 (define_mode_iterator VEC_64 [V2DI V2DF])
@@ -71,13 +78,9 @@
 (define_mode_iterator VI [V4SI V8HI V16QI])
 
 ;; Base type from vector mode
-(define_mode_attr VEC_base [(V32QI "QI")
-			    (V16QI "QI")
-			    (V16HI "HI")
+(define_mode_attr VEC_base [(V16QI "QI")
 			    (V8HI  "HI")
-			    (V8SI  "SI")
 			    (V4SI  "SI")
-			    (V4DI  "DI")
 			    (V2DI  "DI")
 			    (V8SF  "SF")
 			    (V4SF  "SF")
@@ -91,7 +94,9 @@
 			      (V8HI  "hi")
 			      (V4SI  "si")
 			      (V2DI  "di")
+			      (V8SF  "sf")
 			      (V4SF  "sf")
+			      (V4DF  "df")
 			      (V2DF  "df")
 			      (V1TI  "ti")
 			      (TI    "ti")])
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 2ef5eb88428..7d732e0db9e 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -213,20 +213,14 @@
 
 ;; Mode attribute to give the correct predicate for ISA 3.0 vector extract and
 ;; insert to validate the operand number.
-(define_mode_attr VSX_EXTRACT_PREDICATE [(V32QI "const_0_to_31_operand")
-					 (V16QI "const_0_to_15_operand")
-					 (V16HI "const_0_to_15_operand")
+(define_mode_attr VSX_EXTRACT_PREDICATE [(V16QI "const_0_to_15_operand")
 					 (V8HI  "const_0_to_7_operand")
-					 (V8SI  "const_0_to_7_operand")
 					 (V4SI  "const_0_to_3_operand")])
 
 ;; Mode attribute to give the constraint for vector extract and insert
 ;; operations.
-(define_mode_attr VSX_EX [(V32QI "v")
-			  (V16QI "v")
-			  (V16HI "v")
+(define_mode_attr VSX_EX [(V16QI "v")
 			  (V8HI  "v")
-			  (V8SI  "wa")
 			  (V4SI  "wa")])
 
 ;; Mode iterator for binary floating types other than double to
@@ -265,30 +259,6 @@
 ;; and Vector Integer Multiply/Divide/Modulo Instructions
 (define_mode_iterator VIlong [V2DI V4SI])
 
-;; Iterator for extraction from vector pair modes with 64-bit elemenents
-(define_mode_iterator VPAIR_V4DI_V4DF [V4DI V4DF])
-
-;; Iterator for the small integer vector pair modes
-(define_mode_iterator VPAIR_SMALL_INT [V32QI V16HI V8SI])
-
-;; Map vector pair mode to vector mode in upper case after the vector pair is
-;; split to two vectors.
-(define_mode_attr VPAIR_VECTOR [(V32QI "V16QI")
-				(V16HI "V8HI")
-				(V8SI  "V4SI")
-				(V4DI  "V2DI")
-				(V8SF  "V4SF")
-				(V4DF  "V2DF")])
-
-;; Map vector pair mode to vector mode in lower case after the vector pair is
-;; split to two vectors.
-(define_mode_attr vpair_vector [(V32QI "v16qi")
-				(V16HI "v8hi")
-				(V8SI  "v4si")
-				(V4DI  "v2di")
-				(V8SF  "v4sf")
-				(V4DF  "v2df")])
-
 ;; Constants for creating unspecs
 (define_c_enum "unspec"
   [UNSPEC_VSX_CONCAT
@@ -3575,18 +3545,18 @@
 }
   [(set_attr "type" "fpload,load")])
 
-;; Exctract DF/DI from V4DF/V4DI, convert it into extract from V2DF/V2DI.
-(define_insn_and_split "vsx_extract_<mode>"
-  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=wa,r")
-	(vec_select:<VEC_base>
-	 (match_operand:VPAIR_V4DI_V4DF 1 "gpc_reg_operand" "wa,wa")
+;; Exctract DF from V4DF, convert it into extract from V2DF.
+(define_insn_and_split "vsx_extract_v4df"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=wa,r")
+	(vec_select:DF
+	 (match_operand:V4DF 1 "gpc_reg_operand" "wa,wa")
 	 (parallel
 	  [(match_operand:QI 2 "const_0_to_3_operand" "n,n")])))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
   [(set (match_dup 0)
-	(vec_select:<VEC_base>
+	(vec_select:DF
 	 (match_dup 3)
 	 (parallel [(match_dup 4)])))]
 {
@@ -3597,7 +3567,7 @@
       || (!WORDS_BIG_ENDIAN && element < 2))
     reg_num++;
 
-  operands[3] = gen_rtx_REG (<VPAIR_VECTOR>mode, reg_num);
+  operands[3] = gen_rtx_REG (V2DFmode, reg_num);
   operands[4] = GEN_INT (element & 1);
 }
   [(set_attr "type" "mfvsr,vecperm")])
@@ -4160,36 +4130,6 @@
 }
   [(set_attr "type" "load")])
 
-;; Extract SI/HI/QI from V8SI/V16HI/V32QI, converting it into an extract from a
-;; single vector.
-(define_insn_and_split "vsx_extract_<mode>"
-  [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,<VSX_EX>")
-	(vec_select:<VEC_base>
-	 (match_operand:VPAIR_SMALL_INT 1 "gpc_reg_operand" "v,<VSX_EX>")
-	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
-   (clobber (match_scratch:SI 3 "=r,X"))]
-  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
-  "#"
-  "&& reload_completed"
-  [(parallel [(set (match_dup 0)
-		   (vec_select:<VEC_base>
-		    (match_dup 4)
-		    (parallel [(match_dup 5)])))
-	      (match_dup 3)])]
-{
-  HOST_WIDE_INT element = INTVAL (operands[2]);
-  HOST_WIDE_INT nunits = GET_MODE_NUNITS (<VPAIR_VECTOR>mode);
-  unsigned reg_num = reg_or_subregno (operands[1]);
-
-  if ((WORDS_BIG_ENDIAN && element >= nunits)
-      || (!WORDS_BIG_ENDIAN && element < nunits))
-    reg_num++;
-
-  operands[4] = gen_rtx_REG (<VPAIR_VECTOR>mode, reg_num);
-  operands[5] = GEN_INT (element & (nunits - 1));
-}
-  [(set_attr "type" "vecsimple")])
-
 ;; ISA 3.1 extract
 (define_expand "vextractl<mode>"
   [(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-3.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-3.c
deleted file mode 100644
index b1952b046f9..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vector-size-32-3.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */
-
-/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector
-   loads and stores with the -mvector-size-32 option.  This file tests 32-byte
-   vectors with 4 64-bit integer elements.  */
-
-typedef long long vectype_t __attribute__((__vector_size__(32)));
-
-void
-test_add (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 vaddudm, 1 stxvp.  */
-  *dest = *a + *b;
-}
-
-void
-test_sub (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 vsubudm, 1 stxvp.  */
-  *dest = *a - *b;
-}
-
-void
-test_negate (vectype_t *dest,
-	     vectype_t *a)
-{
-  /* 2 lxvp, 2 vnegd, 1 stxvp.  */
-  *dest = - *a;
-}
-
-void
-test_not (vectype_t *dest,
-	  vectype_t *a)
-{
-  /* 2 lxvp, 2 xxlnor, 1 stxvp.  */
-  *dest = ~ *a;
-}
-
-void
-test_and (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 xxland, 1 stxvp.  */
-  *dest = *a & *b;
-}
-
-void
-test_or (vectype_t *dest,
-	 vectype_t *a,
-	 vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlor, 1 stxvp.  */
-  *dest = *a | *b;
-}
-
-void
-test_xor (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlxor, 1 stxvp.  */
-  *dest = *a ^ *b;
-}
-
-void
-test_andc_1 (vectype_t *dest,
-	     vectype_t *a,
-	     vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlandc, 1 stxvp.  */
-  *dest = (~ *a) & *b;
-}
-
-void
-test_andc_2 (vectype_t *dest,
-	     vectype_t *a,
-	     vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlandc, 1 stxvp.  */
-  *dest = *a & (~ *b);
-}
-
-void
-test_orc_1 (vectype_t *dest,
-	    vectype_t *a,
-	    vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlorc, 1 stxvp.  */
-  *dest = (~ *a) | *b;
-}
-
-void
-test_orc_2 (vectype_t *dest,
-	    vectype_t *a,
-	    vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlorc, 1 stxvp.  */
-  *dest = *a | (~ *b);
-}
-
-void
-test_nand (vectype_t *dest,
-	   vectype_t *a,
-	   vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlnand, 1 stxvp.  */
-  *dest = ~(*a & *b);
-}
-
-void
-test_nor (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlnor, 1 stxvp.  */
-  *dest = ~(*a | *b);
-}
-
-/* { dg-final { scan-assembler-times {\mlxvp\M}    24 } } */
-/* { dg-final { scan-assembler-times {\mstxvp\M}   13 } } */
-/* { dg-final { scan-assembler-times {\mvaddudm\M}  2 } } */
-/* { dg-final { scan-assembler-times {\mvnegd\M}    2 } } */
-/* { dg-final { scan-assembler-times {\mvsubudm\M}  2 } } */
-/* { dg-final { scan-assembler-times {\mxxland\M}   2 } } */
-/* { dg-final { scan-assembler-times {\mxxlandc\M}  4 } } */
-/* { dg-final { scan-assembler-times {\mxxlnand\M}  2 } } */
-/* { dg-final { scan-assembler-times {\mxxlnor\M}   4 } } */
-/* { dg-final { scan-assembler-times {\mxxlor\M}    2 } } */
-/* { dg-final { scan-assembler-times {\mxxlorc\M}   4 } } */
-/* { dg-final { scan-assembler-times {\mxxlxor\M}   2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-4.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-4.c
deleted file mode 100644
index 110292bb4df..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vector-size-32-4.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */
-
-/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector
-   loads and stores with the -mvector-size-32 option.  This file tests 32-byte
-   vectors with 4 64-bit integer elements.  */
-
-typedef int vectype_t __attribute__((__vector_size__(32)));
-
-void
-test_add (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 vadduwm, 1 stxvp.  */
-  *dest = *a + *b;
-}
-
-void
-test_sub (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 vsubuwm, 1 stxvp.  */
-  *dest = *a - *b;
-}
-
-void
-test_negate (vectype_t *dest,
-	     vectype_t *a)
-{
-  /* 2 lxvp, 2 vnegw, 1 stxvp.  */
-  *dest = - *a;
-}
-
-void
-test_not (vectype_t *dest,
-	  vectype_t *a)
-{
-  /* 2 lxvp, 2 xxlnor, 1 stxvp.  */
-  *dest = ~ *a;
-}
-
-void
-test_and (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 xxland, 1 stxvp.  */
-  *dest = *a & *b;
-}
-
-void
-test_or (vectype_t *dest,
-	 vectype_t *a,
-	 vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlor, 1 stxvp.  */
-  *dest = *a | *b;
-}
-
-void
-test_xor (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlxor, 1 stxvp.  */
-  *dest = *a ^ *b;
-}
-
-void
-test_andc_1 (vectype_t *dest,
-	     vectype_t *a,
-	     vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlandc, 1 stxvp.  */
-  *dest = (~ *a) & *b;
-}
-
-void
-test_andc_2 (vectype_t *dest,
-	     vectype_t *a,
-	     vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlandc, 1 stxvp.  */
-  *dest = *a & (~ *b);
-}
-
-void
-test_orc_1 (vectype_t *dest,
-	    vectype_t *a,
-	    vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlorc, 1 stxvp.  */
-  *dest = (~ *a) | *b;
-}
-
-void
-test_orc_2 (vectype_t *dest,
-	    vectype_t *a,
-	    vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlorc, 1 stxvp.  */
-  *dest = *a | (~ *b);
-}
-
-void
-test_nand (vectype_t *dest,
-	   vectype_t *a,
-	   vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlnand, 1 stxvp.  */
-  *dest = ~(*a & *b);
-}
-
-void
-test_nor (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlnor, 1 stxvp.  */
-  *dest = ~(*a | *b);
-}
-
-/* { dg-final { scan-assembler-times {\mlxvp\M}    24 } } */
-/* { dg-final { scan-assembler-times {\mstxvp\M}   13 } } */
-/* { dg-final { scan-assembler-times {\mvadduwm\M}  2 } } */
-/* { dg-final { scan-assembler-times {\mvnegw\M}    2 } } */
-/* { dg-final { scan-assembler-times {\mvsubuwm\M}  2 } } */
-/* { dg-final { scan-assembler-times {\mxxland\M}   2 } } */
-/* { dg-final { scan-assembler-times {\mxxlandc\M}  4 } } */
-/* { dg-final { scan-assembler-times {\mxxlnand\M}  2 } } */
-/* { dg-final { scan-assembler-times {\mxxlnor\M}   4 } } */
-/* { dg-final { scan-assembler-times {\mxxlor\M}    2 } } */
-/* { dg-final { scan-assembler-times {\mxxlorc\M}   4 } } */
-/* { dg-final { scan-assembler-times {\mxxlxor\M}   2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-5.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-5.c
deleted file mode 100644
index 8921b04c468..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vector-size-32-5.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */
-
-/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector
-   loads and stores with the -mvector-size-32 option.  This file tests 32-byte
-   vectors with 4 64-bit integer elements.  */
-
-typedef short vectype_t __attribute__((__vector_size__(32)));
-
-void
-test_add (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 vadduhm, 1 stxvp.  */
-  *dest = *a + *b;
-}
-
-void
-test_sub (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 vsubuhm, 1 stxvp.  */
-  *dest = *a - *b;
-}
-
-void
-test_negate (vectype_t *dest,
-	     vectype_t *a)
-{
-  /* 2 lxvp, 1 xxspltib, 2 vsubuhm, 1 stxvp.  */
-  *dest = - *a;
-}
-
-void
-test_not (vectype_t *dest,
-	  vectype_t *a)
-{
-  /* 2 lxvp, 2 xxlnor, 1 stxvp.  */
-  *dest = ~ *a;
-}
-
-void
-test_and (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 xxland, 1 stxvp.  */
-  *dest = *a & *b;
-}
-
-void
-test_or (vectype_t *dest,
-	 vectype_t *a,
-	 vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlor, 1 stxvp.  */
-  *dest = *a | *b;
-}
-
-void
-test_xor (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlxor, 1 stxvp.  */
-  *dest = *a ^ *b;
-}
-
-void
-test_andc_1 (vectype_t *dest,
-	     vectype_t *a,
-	     vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlandc, 1 stxvp.  */
-  *dest = (~ *a) & *b;
-}
-
-void
-test_andc_2 (vectype_t *dest,
-	     vectype_t *a,
-	     vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlandc, 1 stxvp.  */
-  *dest = *a & (~ *b);
-}
-
-void
-test_orc_1 (vectype_t *dest,
-	    vectype_t *a,
-	    vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlorc, 1 stxvp.  */
-  *dest = (~ *a) | *b;
-}
-
-void
-test_orc_2 (vectype_t *dest,
-	    vectype_t *a,
-	    vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlorc, 1 stxvp.  */
-  *dest = *a | (~ *b);
-}
-
-void
-test_nand (vectype_t *dest,
-	   vectype_t *a,
-	   vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlnand, 1 stxvp.  */
-  *dest = ~(*a & *b);
-}
-
-void
-test_nor (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlnor, 1 stxvp.  */
-  *dest = ~(*a | *b);
-}
-
-/* { dg-final { scan-assembler-times {\mlxvp\M}     24 } } */
-/* { dg-final { scan-assembler-times {\mstxvp\M}    13 } } */
-/* { dg-final { scan-assembler-times {\mvadduhm\M}   2 } } */
-/* { dg-final { scan-assembler-times {\mvsubuhm\M}   4 } } */
-/* { dg-final { scan-assembler-times {\mxxland\M}    2 } } */
-/* { dg-final { scan-assembler-times {\mxxlandc\M}   4 } } */
-/* { dg-final { scan-assembler-times {\mxxlnand\M}   2 } } */
-/* { dg-final { scan-assembler-times {\mxxlnor\M}    4 } } */
-/* { dg-final { scan-assembler-times {\mxxlor\M}     2 } } */
-/* { dg-final { scan-assembler-times {\mxxlorc\M}    4 } } */
-/* { dg-final { scan-assembler-times {\mxxlxor\M}    2 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M}  1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-6.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-6.c
deleted file mode 100644
index a905e6b0a31..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vector-size-32-6.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */
-
-/* Test whether the __attrbiute__((__vector_size(32))) generates paired vector
-   loads and stores with the -mvector-size-32 option.  This file tests 32-byte
-   vectors with 4 64-bit integer elements.  */
-
-typedef unsigned char vectype_t __attribute__((__vector_size__(32)));
-
-void
-test_add (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 vaddubm, 1 stxvp.  */
-  *dest = *a + *b;
-}
-
-void
-test_sub (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 vsububm, 1 stxvp.  */
-  *dest = *a - *b;
-}
-
-void
-test_negate (vectype_t *dest,
-	     vectype_t *a)
-{
-  /* 2 lxvp, 1 xxspltib, 2 vsububm, 1 stxvp.  */
-  *dest = - *a;
-}
-
-void
-test_not (vectype_t *dest,
-	  vectype_t *a)
-{
-  /* 2 lxvp, 2 xxlnor, 1 stxvp.  */
-  *dest = ~ *a;
-}
-
-void
-test_and (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 xxland, 1 stxvp.  */
-  *dest = *a & *b;
-}
-
-void
-test_or (vectype_t *dest,
-	 vectype_t *a,
-	 vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlor, 1 stxvp.  */
-  *dest = *a | *b;
-}
-
-void
-test_xor (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlxor, 1 stxvp.  */
-  *dest = *a ^ *b;
-}
-
-void
-test_andc_1 (vectype_t *dest,
-	     vectype_t *a,
-	     vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlandc, 1 stxvp.  */
-  *dest = (~ *a) & *b;
-}
-
-void
-test_andc_2 (vectype_t *dest,
-	     vectype_t *a,
-	     vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlandc, 1 stxvp.  */
-  *dest = *a & (~ *b);
-}
-
-void
-test_orc_1 (vectype_t *dest,
-	    vectype_t *a,
-	    vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlorc, 1 stxvp.  */
-  *dest = (~ *a) | *b;
-}
-
-void
-test_orc_2 (vectype_t *dest,
-	    vectype_t *a,
-	    vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlorc, 1 stxvp.  */
-  *dest = *a | (~ *b);
-}
-
-void
-test_nand (vectype_t *dest,
-	   vectype_t *a,
-	   vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlnand, 1 stxvp.  */
-  *dest = ~(*a & *b);
-}
-
-void
-test_nor (vectype_t *dest,
-	  vectype_t *a,
-	  vectype_t *b)
-{
-  /* 2 lxvp, 2 xxlnor, 1 stxvp.  */
-  *dest = ~(*a | *b);
-}
-
-/* { dg-final { scan-assembler-times {\mlxvp\M}      24 } } */
-/* { dg-final { scan-assembler-times {\mstxvp\M}     13 } } */
-/* { dg-final { scan-assembler-times {\mvaddubm\M}    2 } } */
-/* { dg-final { scan-assembler-times {\mvsububm\M}    4 } } */
-/* { dg-final { scan-assembler-times {\mxxland\M}     2 } } */
-/* { dg-final { scan-assembler-times {\mxxlandc\M}    4 } } */
-/* { dg-final { scan-assembler-times {\mxxlnand\M}    2 } } */
-/* { dg-final { scan-assembler-times {\mxxlnor\M}     4 } } */
-/* { dg-final { scan-assembler-times {\mxxlor\M}      2 } } */
-/* { dg-final { scan-assembler-times {\mxxlorc\M}     4 } } */
-/* { dg-final { scan-assembler-times {\mxxlxor\M}     2 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M}   1 } } */

^ permalink raw reply	[flat|nested] only message in thread

only message in thread, other threads:[~2023-11-17  3:52 UTC | newest]

Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-17  3:52 [gcc(refs/users/meissner/heads/work144-vsubreg)] Sync vsize patches 401 - 404 Michael Meissner

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).