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* [gcc(refs/users/meissner/heads/work144-vsize)] Add some integer vector pair support.
@ 2023-11-17 16:21 Michael Meissner
  0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2023-11-17 16:21 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:d3df605932cc8edc96345237262ecd7687c49800

commit d3df605932cc8edc96345237262ecd7687c49800
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Nov 17 11:20:44 2023 -0500

    Add some integer vector pair support.
    
    2023-11-16  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vector-pair.md (VPAIR_INT): Rename from VPAIR_LOGICAL.
            (VPAIR_NEG_VNEG): New mode iterator.
            (VPAIR_NEG_SUB): Likewise.
            (VPAIR_INT_BINARY): Likewise.
            (vpair_op): Fix standard name for not.
            (vec_init<mode><vpair_element_l>): Use vsx_register_operand.
            (neg<mode>2, VPAIR_NEG_VNEG iterator): New insn.
            (neg<mode>2, VPAIR_NEG_SUB): Likewise.
            (vector pair integer ops): Update iterators.  Add add, subtract, min,
            max, and negate support.

Diff:
---
 gcc/config/rs6000/rs6000.cc | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 6f94bd204a5..2f93f508a1a 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -5216,6 +5216,15 @@ rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
 static machine_mode
 rs6000_preferred_simd_mode (scalar_mode mode)
 {
+  /* Prefer vector pair for floating point, but not for integer modes.  */
+  if (TARGET_MMA && TARGET_VECTOR_SIZE_32)
+    {
+      if (mode == DFmode)
+	return V4DFmode;
+      else if (mode == SFmode)
+	return V8SFmode;
+    }
+
   opt_machine_mode vmode = mode_for_vector (mode, 16 / GET_MODE_SIZE (mode));
 
   if (vmode.exists () && !VECTOR_MEM_NONE_P (vmode.require ()))

^ permalink raw reply	[flat|nested] 2+ messages in thread

* [gcc(refs/users/meissner/heads/work144-vsize)] Add some integer vector pair support.
@ 2023-11-17  3:45 Michael Meissner
  0 siblings, 0 replies; 2+ messages in thread
From: Michael Meissner @ 2023-11-17  3:45 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:9fb2839f1d6b0e2174142e792aa356859e19739b

commit 9fb2839f1d6b0e2174142e792aa356859e19739b
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Nov 16 22:45:11 2023 -0500

    Add some integer vector pair support.
    
    2023-11-16  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vector-pair.md (VPAIR_INT): Rename from VPAIR_LOGICAL.
            (VPAIR_NEG_VNEG): New mode iterator.
            (VPAIR_NEG_SUB): Likewise.
            (VPAIR_INT_BINARY): Likewise.
            (vpair_op): Fix standard name for not.
            (vec_init<mode><vpair_element_l>): Use vsx_register_operand.
            (neg<mode>2, VPAIR_NEG_VNEG iterator): New insn.
            (neg<mode>2, VPAIR_NEG_SUB): Likewise.
            (vector pair integer ops): Update iterators.  Add add, subtract, min,
            max, and negate support.

Diff:
---
 gcc/config/rs6000/vector-pair.md | 153 ++++++++++++++++++++++++++-------------
 1 file changed, 103 insertions(+), 50 deletions(-)

diff --git a/gcc/config/rs6000/vector-pair.md b/gcc/config/rs6000/vector-pair.md
index 60a3502169b..51b93a43ab0 100644
--- a/gcc/config/rs6000/vector-pair.md
+++ b/gcc/config/rs6000/vector-pair.md
@@ -40,12 +40,20 @@
 
 ;; Integer vector pair ops.  We need the basic logical opts to support
 ;; permution on little endian systems.
-(define_mode_iterator VPAIR_LOGICAL [V32QI V16HI V8SI V4DI])
+(define_mode_iterator VPAIR_INT [V32QI V16HI V8SI V4DI])
 
-;; Iterator for logical unary/binary operations.
+;; Special iterators for NEG (V4SI and V2DI have vneg{w,d}), while V16QI and
+;; V8HI have to use a subtract from 0.
+(define_mode_iterator VPAIR_NEG_VNEG [V4DI V8SI])
+(define_mode_iterator VPAIR_NEG_SUB [V32QI V16HI])
+
+;; Iterator integer unary/binary operations.  Logical operations can be done on
+;; all VSX registers, while the binary int operators need Altivec registers.
 (define_code_iterator VPAIR_LOGICAL_UNARY  [not])
 (define_code_iterator VPAIR_LOGICAL_BINARY [and ior xor])
 
+(define_code_iterator VPAIR_INT_BINARY     [plus minus smin smax])
+
 ;; Give the insn name from the opertion
 (define_code_attr vpair_op [(abs   "abs")
 			    (div   "div")
@@ -55,7 +63,7 @@
 			    (minus "sub")
 			    (mult  "mul")
 			    (neg   "neg")
-			    (not   "not")
+			    (not   "one_cmpl")
 			    (plus  "add")
 			    (smin  "smin")
 			    (smax  "smax")
@@ -148,7 +156,7 @@
 \f
 ;; Vector pair initialization
 (define_expand "vec_init<mode><vpair_element_l>"
-  [(match_operand:VPAIR 0 "vlogical_operand")
+  [(match_operand:VPAIR 0 "vsx_register_operand")
    (match_operand:VPAIR 1 "")]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
 {
@@ -158,7 +166,7 @@
 
 ;; Vector pair set element
 (define_expand "vec_set<mode>"
-  [(match_operand:VPAIR 0 "vlogical_operand")
+  [(match_operand:VPAIR 0 "vsx_register_operand")
    (match_operand:<VPAIR_ELEMENT> 1 "register_operand")
    (match_operand 2 "vec_set_index_operand")]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
@@ -490,11 +498,56 @@
 }
   [(set_attr "length" "8")])
 \f
-;; Vector pair integer unary operations
+;; Vector pair negate if we have the VNEGx instruction.
+(define_insn_and_split "neg<mode>2"
+  [(set (match_operand:VPAIR_NEG_VNEG 0 "vsx_register_operand" "=v")
+	(neg:VPAIR_NEG_VNEG
+	 (match_operand:VPAIR_NEG_VNEG 1 "vsx_register_operand" "v")))]
+  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+{
+  split_unary_vector_pair (<VPAIR_VECTOR>mode, operands,
+			   gen_neg<vpair_vector_l>2);
+  DONE;
+}
+  [(set_attr "length" "8")])
+
+;; Vector pair negate if we have to do a subtract from 0
+(define_insn_and_split "neg<mode>2"
+  [(set (match_operand:VPAIR_NEG_SUB 0 "vsx_register_operand" "=v")
+	(neg:VPAIR_NEG_SUB
+	 (match_operand:VPAIR_NEG_SUB 1 "vsx_register_operand" "v")))
+   (clobber (match_scratch:<VPAIR_VECTOR> 2 "=&v"))]
+  "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+{
+  enum machine_mode mode = <VPAIR_VECTOR>mode;
+  rtx tmp = operands[2];
+  unsigned reg0 = reg_or_subregno (operands[0]);
+  unsigned reg1 = reg_or_subregno (operands[1]);
+
+  emit_move_insn (tmp, CONST0_RTX (mode));
+  emit_insn (gen_sub<vpair_vector_l>3 (gen_rtx_REG (mode, reg0),
+				       tmp,
+				       gen_rtx_REG (mode, reg1)));
+
+  emit_insn (gen_sub<vpair_vector_l>3 (gen_rtx_REG (mode, reg0 + 1),
+				       tmp,
+				       gen_rtx_REG (mode, reg1 + 1)));
+
+  DONE;
+}
+  [(set_attr "length" "8")])
+
+;; Vector pair logical unary operations
 (define_insn_and_split "<vpair_op><mode>2"
-  [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
-	(VPAIR_FP_UNARY:VPAIR_LOGICAL
-	 (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa")))]
+  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
+	(VPAIR_LOGICAL_UNARY:VPAIR_INT
+	 (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -508,10 +561,10 @@
 
 ;; Vector pair logical binary operations
 (define_insn_and_split "<vpair_op><mode>3"
-  [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
-	(VPAIR_FP_BINARY:VPAIR_LOGICAL
-	 (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa")
-	 (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa")))]
+  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
+	(VPAIR_LOGICAL_BINARY:VPAIR_INT
+	 (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")
+	 (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa")))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -525,11 +578,11 @@
 
 ;; Optiomize vector pair ~(a | b)  or ((~a) & (~b)) to produce xxlnor
 (define_insn_and_split "*nor<mode>3_1"
-  [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
-	(not:VPAIR_LOGICAL
-	 (ior:VPAIR_LOGICAL
-	  (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa")
-	  (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa"))))]
+  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
+	(not:VPAIR_INT
+	 (ior:VPAIR_INT
+	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")
+	  (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -542,12 +595,12 @@
   [(set_attr "length" "8")])
 
 (define_insn_and_split "*nor<mode>3_2"
-  [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
-	(and:VPAIR_LOGICAL
-	 (not:VPAIR_LOGICAL
-	  (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa"))
-	 (not:VPAIR_LOGICAL
-	  (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa"))))]
+  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
+	(and:VPAIR_INT
+	 (not:VPAIR_INT
+	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa"))
+	 (not:VPAIR_INT
+	  (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -561,11 +614,11 @@
 
 ;; Optimize vector pair (~a) & b to use xxlandc
 (define_insn_and_split "*andc<mode>3"
-  [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
-	(and:VPAIR_LOGICAL
-	 (not:VPAIR_LOGICAL
-	  (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa"))
-	 (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa")))]
+  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
+	(and:VPAIR_INT
+	 (not:VPAIR_INT
+	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa"))
+	 (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa")))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -579,11 +632,11 @@
 
 ;; Optimize vector pair ~(a ^ b) to produce xxleqv
 (define_insn_and_split "*eqv<mode>3"
-  [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
-	(not:VPAIR_LOGICAL
-	 (xor:VPAIR_LOGICAL
-	  (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa")
-	  (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa"))))]
+  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
+	(not:VPAIR_INT
+	 (xor:VPAIR_INT
+	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")
+	  (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -598,11 +651,11 @@
 
 ;; Optiomize vector pair ~(a & b) or ((~a) | (~b)) to produce xxlnand
 (define_insn_and_split "*nand<mode>3_1"
-  [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
-	(not:VPAIR_LOGICAL
-	 (and:VPAIR_LOGICAL
-	  (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa")
-	  (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa"))))]
+  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
+	(not:VPAIR_INT
+	 (and:VPAIR_INT
+	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa")
+	  (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -615,12 +668,12 @@
   [(set_attr "length" "8")])
 
 (define_insn_and_split "*nand<mode>3_2"
-  [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
-	(ior:VPAIR_LOGICAL
-	 (not:VPAIR_LOGICAL
-	  (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa"))
-	 (not:VPAIR_LOGICAL
-	  (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa"))))]
+  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
+	(ior:VPAIR_INT
+	 (not:VPAIR_INT
+	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa"))
+	 (not:VPAIR_INT
+	  (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa"))))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
@@ -634,11 +687,11 @@
 
 ;; Optimize vector pair (~a) | b to produce xxlorc
 (define_insn_and_split "*orc<mode>3"
-  [(set (match_operand:VPAIR_LOGICAL 0 "vsx_register_operand" "=wa")
-	(ior:VPAIR_LOGICAL
-	 (not:VPAIR_LOGICAL
-	  (match_operand:VPAIR_LOGICAL 1 "vsx_register_operand" "wa"))
-	 (match_operand:VPAIR_LOGICAL 2 "vsx_register_operand" "wa")))]
+  [(set (match_operand:VPAIR_INT 0 "vsx_register_operand" "=wa")
+	(ior:VPAIR_INT
+	 (not:VPAIR_INT
+	  (match_operand:VPAIR_INT 1 "vsx_register_operand" "wa"))
+	 (match_operand:VPAIR_INT 2 "vsx_register_operand" "wa")))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"

^ permalink raw reply	[flat|nested] 2+ messages in thread

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