[gcc(refs/users/meissner/heads/work146-vsubreg)] Add set/extract support on vector pairs with double word elements.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:18bded04cb2f7825d5abee118cd3e42541bd377c

commit 18bded04cb2f7825d5abee118cd3e42541bd377c
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Sat Nov 18 17:58:04 2023 -0500

    Add set/extract support on vector pairs with double word elements.
    
    2023-11-18  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000-protos.h (rs6000_expand_vector_pair_set): Delete.
            * config/rs6000/rs6000.cc (rs6000_expand_vector_pair_set): Likewise.
            * config/rs6000/vector-pair.md (vec_set<mode>): Replace with a version
            that only handles setting double word elements.
            (vec_extract<mode><vpair_element_l>): Likewise.

Diff:
---
 gcc/config/rs6000/rs6000-protos.h |  1 -
 gcc/config/rs6000/rs6000.cc       |  9 ------
 gcc/config/rs6000/vector-pair.md  | 66 +++++++++++++++++++++++++++++----------
 3 files changed, 50 insertions(+), 26 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 13687c5b1b3..27f1f41dacd 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -63,7 +63,6 @@ extern void rs6000_expand_float128_convert (rtx, rtx, bool);
 extern void rs6000_expand_vector_init (rtx, rtx);
 extern void rs6000_expand_vector_pair_init (rtx, rtx);
 extern void rs6000_expand_vector_set (rtx, rtx, rtx);
-extern void rs6000_expand_vector_pair_set (rtx, rtx, rtx);
 extern void rs6000_expand_vector_extract (rtx, rtx, rtx);
 extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx);
 extern rtx rs6000_adjust_vec_address (rtx, rtx, rtx, rtx, machine_mode);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index d3aecb68565..b597f51a833 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7813,15 +7813,6 @@ rs6000_expand_vector_set (rtx target, rtx val, rtx elt_rtx)
   emit_insn (gen_rtx_SET (target, x));
 }
 
-/* Set field ELT_RTX of vaector pair TARGET to VAL.  */
-
-void
-rs6000_expand_vector_pair_set (rtx target, rtx val, rtx elt_rtx)
-{
-  if (target || val || elt_rtx)
-    gcc_unreachable ();
-}
-
 /* Extract field ELT from VEC into TARGET.  */
 
 void
diff --git a/gcc/config/rs6000/vector-pair.md b/gcc/config/rs6000/vector-pair.md
index 15d897906bd..cbbb6f95a3a 100644
--- a/gcc/config/rs6000/vector-pair.md
+++ b/gcc/config/rs6000/vector-pair.md
@@ -54,6 +54,9 @@
 
 (define_code_iterator VPAIR_INT_BINARY     [plus minus smin smax umin umax])
 
+;; Iterator for vector pairs with double word elements
+(define_mode_iterator VPAIR_DWORD [V4DI V4DF])
+
 ;; Give the insn name from the opertion
 (define_code_attr vpair_op [(abs   "abs")
 			    (div   "div")
@@ -167,30 +170,61 @@
   DONE;
 })
 
-;; Vector pair set element
-(define_expand "vec_set<mode>"
-  [(match_operand:VPAIR 0 "vsx_register_operand")
-   (match_operand:<VPAIR_ELEMENT> 1 "register_operand")
-   (match_operand 2 "vec_set_index_operand")]
+;; Set an element in a vector pair with double word elements.
+(define_insn_and_split "vec_set<mode>"
+  [(set (match_operand:VPAIR_DWORD 0 "vsx_register_operand" "+&wa")
+	(unspec:VPAIR_DWORD
+	 [(match_dup 0)
+	  (match_operand:<VPAIR_ELEMENT> 1 "vsx_register_operand" "wa")
+	  (match_operand 2 "const_0_to_3_operand" "n")]
+	 UNSPEC_VSX_SET))
+   (clobber (match_scratch:<VPAIR_ELEMENT> 3 "=&wa"))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
 {
-  rs6000_expand_vector_pair_set (operands[0], operands[1], operands[2]);
+  rtx dest = operands[0];
+  rtx value = operands[1];
+  HOST_WIDE_INT elt = INTVAL (operands[2]);
+  rtx tmp = operands[3];
+  machine_mode mode = <MODE>mode;
+  machine_mode vmode = <VPAIR_VECTOR>mode;
+  unsigned vsize = GET_MODE_SIZE (<VPAIR_VECTOR>mode);
+  unsigned reg_num = ((WORDS_BIG_ENDIAN && elt >= vsize)
+		      || (!WORDS_BIG_ENDIAN && elt < vsize));
+	   
+  rtx vreg = simplify_gen_subreg (vmode, dest, mode, reg_num * 16);
+
+  if ((elt & 0x1) == 0)
+    {
+      emit_insn (gen_vsx_extract_<vpair_vector_l> (tmp, vreg, const1_rtx));
+      emit_insn (gen_vsx_concat_<vpair_vector_l> (vreg, value, tmp));
+    }
+  else
+    {
+      emit_insn (gen_vsx_extract_<vpair_vector_l> (tmp, vreg, const0_rtx));
+      emit_insn (gen_vsx_concat_<vpair_vector_l> (vreg, tmp, value));
+    }
+
   DONE;
-})
+}
+  [(set_attr "length" "8")
+   (set_attr "type" "vecperm")])
 
-;; Vector pair extracti element
+;; Extract an element in a vector pair with double word elements
 (define_insn_and_split "vec_extract<mode><vpair_element_l>"
   [(set (match_operand:<VPAIR_ELEMENT> 0 "vsx_register_operand" "=wa")
 	(vec_select:<VPAIR_ELEMENT>
-	 (match_operand:VPAIR 1 "vsx_register_operand" "wa")
-	 (parallel [(match_operand:QI 2 "const_int_operand" "n")])))]
+	 (match_operand:VPAIR_DWORD 1 "vsx_register_operand" "wa")
+	 (parallel [(match_operand 2 "const_0_to_3_operand" "n")])))]
   "TARGET_MMA && TARGET_VECTOR_SIZE_32"
   "#"
   "&& reload_completed"
   [(const_int 0)]
 {
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
+  rtx dest = operands[0];
+  rtx vpair = operands[1];
   HOST_WIDE_INT elt = INTVAL (operands[2]);
   machine_mode mode = <MODE>mode;
   machine_mode vmode = <VPAIR_VECTOR>mode;
@@ -198,12 +232,12 @@
   unsigned reg_num = ((WORDS_BIG_ENDIAN && elt >= vsize)
 		      || (!WORDS_BIG_ENDIAN && elt < vsize));
 	   
-  rtx vreg = simplify_gen_subreg (vmode, op1, mode, reg_num * 16);
-  emit_insn (gen_vsx_extract_<vpair_vector_l> (op0, vreg,
-					       GEN_INT (elt % vsize)));
+  rtx vreg = simplify_gen_subreg (vmode, vpair, mode, reg_num * 16);
+  rtx elt_in_vreg = GEN_INT (elt & 0x1);
+  emit_insn (gen_vsx_extract_<vpair_vector_l> (dest, vreg, elt_in_vreg));
   DONE;
 }
-  [(set_attr "type" "veclogical")])
+  [(set_attr "type" "vecperm")])
 
 ;; Assemble a vector pair from two vectors.
 ;;