[gcc(refs/users/meissner/heads/work146-vsubreg)] Add more vector pair constants.

[gcc(refs/users/meissner/heads/work146-vsubreg)] Add more vector pair constants.

[Michael Meissner]

https://gcc.gnu.org/g:c09e75a403637e0f78c047b67b47d54a01b13b41

commit c09e75a403637e0f78c047b67b47d54a01b13b41
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Sun Nov 19 12:24:55 2023 -0500

    Add more vector pair constants.
    
    2023-11-19  Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/constraints.md (eV): New constraint.
            * config/rs6000/predicates.md (easy_vector_constant): Add support for
            vector pair constants.
            (easy_vector_pair_constant): New predicate.
            * config/rs6000/rs6000-protos.h (vector_pair_to_vector_mode): New
            declaration.
            (split_vector_ppair_constant): Likewise.
            * config/rs6000/rs6000.cc (vector_pair_to_vector_mode): Make global.
            (split_vector_ppair_constant): Make global.  Rename from
            rs6000_split_vector_pair_constant.
            (rs6000_expand_vector_pair_init): Rename split_vector_pair_constant
            call.
            (rs6000_split_multireg_move): Likewise.
            * config/rs6000/vector-pair.md (mov<mode>): Add support for other vector
            pair constants that can be loaded in 2 instructions.
            * doc/md.texi (eV constraint): Document
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vector-size-32-7.c: New test.

Diff:
---
 gcc/config/rs6000/constraints.md                   |  6 ++++
 gcc/config/rs6000/predicates.md                    | 23 +++++++++++++++
 gcc/config/rs6000/rs6000-protos.h                  |  2 ++
 gcc/config/rs6000/rs6000.cc                        | 10 +++----
 gcc/config/rs6000/vector-pair.md                   | 33 +++++++++-------------
 gcc/doc/md.texi                                    |  4 +++
 .../gcc.target/powerpc/vector-size-32-7.c          | 31 ++++++++++++++++++++
 7 files changed, 84 insertions(+), 25 deletions(-)

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index c4a6ccf4efb..f28e7701a4e 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -219,6 +219,12 @@
   "An IEEE 128-bit constant that can be loaded into VSX registers."
   (match_operand 0 "easy_vector_constant_ieee128"))
 
+;; A vector pair constant that can be loaded into registers without using a
+;; load operation.
+(define_constraint "eV"
+  "A vector pair constant that can be loaded into VSX registers."
+  (match_operand 0 "easy_vector_pair_constant"))
+
 ;; Floating-point constraints.  These two are defined so that insn
 ;; length attributes can be calculated exactly.
 
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 8a56487d7d2..1a1ebfd0e72 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -734,6 +734,9 @@
       if (zero_constant (op, mode) || all_ones_constant (op, mode))
 	return true;
 
+      if (VECTOR_PAIR_MODE (mode) && easy_vector_pair_constant (op, mode))
+	return true;
+
       /* Constants that can be generated with ISA 3.1 instructions are
          easy.  */
       vec_const_128bit_type vsx_const;
@@ -764,6 +767,26 @@
   return false;
 })
 
+;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
+;; a pair of vector registers without using memory.
+(define_predicate "easy_vector_pair_constant"
+  (match_code "const_vector")
+{
+  rtx hi_constant, lo_constant;
+  machine_mode vmode;
+
+  if (!TARGET_MMA || !TARGET_VECTOR_SIZE_32 || !VECTOR_PAIR_MODE (mode))
+    return false;
+
+  vmode = vector_pair_to_vector_mode (mode);
+  if (vmode == VOIDmode)
+    return false;
+
+  return (split_vector_pair_constant (op, &hi_constant, &lo_constant)
+	  && easy_vector_constant (hi_constant, vmode)
+	  && easy_vector_constant (lo_constant, vmode));
+})
+
 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
 (define_predicate "easy_vector_constant_add_self"
   (and (match_code "const_vector")
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 27f1f41dacd..dac48f199ab 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -61,6 +61,8 @@ extern bool rs6000_move_128bit_ok_p (rtx []);
 extern bool rs6000_split_128bit_ok_p (rtx []);
 extern void rs6000_expand_float128_convert (rtx, rtx, bool);
 extern void rs6000_expand_vector_init (rtx, rtx);
+extern machine_mode vector_pair_to_vector_mode (machine_mode);
+extern bool split_vector_pair_constant (rtx, rtx *, rtx *);
 extern void rs6000_expand_vector_pair_init (rtx, rtx);
 extern void rs6000_expand_vector_set (rtx, rtx, rtx);
 extern void rs6000_expand_vector_extract (rtx, rtx, rtx);
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index b597f51a833..aeac7c9fa42 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -7351,7 +7351,7 @@ rs6000_expand_vector_init (rtx target, rtx vals)
 
 /* For a vector pair mode, return the equivalent vector mode or VOIDmode.  */
 
-static machine_mode
+machine_mode
 vector_pair_to_vector_mode (machine_mode mode)
 {
   machine_mode vmode;
@@ -7375,8 +7375,8 @@ vector_pair_to_vector_mode (machine_mode mode)
    pair into 2 separate constants that can be held in a single vector register.
    Return true if we can split the constant.  */
 
-static bool
-rs6000_split_vpair_constant (rtx op, rtx *high, rtx *low)
+bool
+split_vector_pair_constant (rtx op, rtx *high, rtx *low)
 {
   machine_mode vmode = vector_pair_to_vector_mode (GET_MODE (op));
 
@@ -7477,7 +7477,7 @@ rs6000_expand_vector_pair_init (rtx target, rtx vals)
   rtx vals_hi;
   rtx vals_lo;
 
-  rs6000_split_vpair_constant (vals, &vals_hi, &vals_lo);
+  split_vector_pair_constant (vals, &vals_hi, &vals_lo);
 
   rs6000_expand_vector_init (vector_hi, vals_hi);
   rs6000_expand_vector_init (vector_lo, vals_lo);
@@ -27761,7 +27761,7 @@ rs6000_split_multireg_move (rtx dst, rtx src)
 
   /* Handle vector pair constants.  */
   if (CONST_VECTOR_P (src) && VECTOR_PAIR_MODE (mode) && TARGET_MMA
-      && rs6000_split_vpair_constant (src, &vpair_hi, &vpair_lo)
+      && split_vector_pair_constant (src, &vpair_hi, &vpair_lo)
       && VSX_REGNO_P (reg))
     {
       reg_mode = GET_MODE (vpair_hi);
diff --git a/gcc/config/rs6000/vector-pair.md b/gcc/config/rs6000/vector-pair.md
index e2bdc376793..dc71ea28293 100644
--- a/gcc/config/rs6000/vector-pair.md
+++ b/gcc/config/rs6000/vector-pair.md
@@ -120,8 +120,11 @@
 })
 
 (define_insn_and_split "*mov<mode>"
-  [(set (match_operand:VPAIR 0 "nonimmediate_operand" "=wa,wa,ZwO,QwO,wa,wa")
-	(match_operand:VPAIR 1 "input_operand" "ZwO,QwO,wa,wa,wa,j"))]
+  [(set (match_operand:VPAIR 0 "nonimmediate_operand"
+				"=wa, wa,   ZwO, QwO, wa, wa, wa")
+
+	(match_operand:VPAIR 1 "input_operand"
+				"ZwO,  QwO, wa,  wa,  wa, j,  eV"))]
   "TARGET_MMA
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
@@ -131,6 +134,7 @@
    stxvp%X0 %x1,%0
    #
    #
+   #
    #"
   "&& reload_completed
    && ((MEM_P (operands[0]) && !TARGET_STORE_VECTOR_PAIR)
@@ -138,27 +142,16 @@
        || (!MEM_P (operands[0]) && !MEM_P (operands[1])))"
   [(const_int 0)]
 {
-  rtx op0 = operands[0];
-  rtx op1 = operands[1];
-
-  if (op1 == CONST0_RTX (<MODE>mode))
-    {
-      machine_mode vmode = <VPAIR_VECTOR>mode;
-      rtx op0_reg0 = simplify_gen_subreg (vmode, op0, <MODE>mode, 0);
-      rtx op0_reg1 = simplify_gen_subreg (vmode, op0, <MODE>mode, 16);
-      rtx zero = CONST0_RTX (vmode);
-      emit_move_insn (op0_reg0, zero);
-      emit_move_insn (op0_reg1, zero);
-      DONE;
-    }
-
   rs6000_split_multireg_move (operands[0], operands[1]);
   DONE;
 }
-  [(set_attr "type" "vecload,vecload,vecstore,vecstore,veclogical,vecperm")
-   (set_attr "size" "256")
-   (set_attr "length" "*,8,*,8,8,8")
-   (set_attr "isa" "lxvp,*,stxvp,*,*,*")])
+  [(set_attr "size" "256")
+   (set_attr "type"   "vecload, vecload, vecstore, vecstore, veclogical,
+                       vecperm, vecperm")
+   (set_attr "length" "*,       8,       *,        8,        8,
+                       8,       24")
+   (set_attr "isa"    "lxvp,    *,       stxvp,    *,        *,
+                       *,       *")])
 \f
 ;; Vector pair initialization
 (define_expand "vec_init<mode><vpair_element_l>"
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index e01cdcbe22c..23c151f90de 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3509,6 +3509,10 @@ loaded to a VSX register with one prefixed instruction.
 An IEEE 128-bit constant that can be loaded into a VSX register with
 the @code{lxvkq} instruction.
 
+@item eV
+A vector pair constant that can be loaded to a VSX register with two
+separate instructions.
+
 @ifset INTERNALS
 @item G
 A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-size-32-7.c b/gcc/testsuite/gcc.target/powerpc/vector-size-32-7.c
new file mode 100644
index 00000000000..a6e8582ba4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vector-size-32-7.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2 -mvector-size-32" } */
+
+/* Test whether we can load vector pair constants into registers without using
+   a load instruction.  */
+
+typedef double vectype_t __attribute__((__vector_size__(32)));
+
+void
+zero (vectype_t *p)
+{
+  *p = (vectype_t) { 0.0, 0.0, 0.0, 0.0 };
+}
+
+void
+one (vectype_t *p)
+{
+  *p = (vectype_t) { 1.0, 1.0, 1.0, 1.0 };
+}
+
+void
+mixed (vectype_t *p)
+{
+  *p = (vectype_t) { 0.0, 0.0, 1.0, 1.0 };
+}
+
+/* { dg-final { scan-assembler-not   {\mp?lxvpx?\M}    } } */
+/* { dg-final { scan-assembler-times {\mp?stxvpx?\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltib\M}  3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */