[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: vsetvl: Refine REG_EQUAL equality.

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: vsetvl: Refine REG_EQUAL equality.

[Jeff Law]

https://gcc.gnu.org/g:7bd3112d8c35e557f9b3f09ec583a49d9e0a9b0e

commit 7bd3112d8c35e557f9b3f09ec583a49d9e0a9b0e
Author: Robin Dapp <rdapp@ventanamicro.com>
Date:   Sat Nov 11 12:47:57 2023 +0100

    RISC-V: vsetvl: Refine REG_EQUAL equality.
    
    This patch enhances the equality check for REG_EQUAL notes in the vsetvl
    pass by using the == operator instead of rtx_equal_p.  With that, in
    situations like the following, a5 and a7 are not considered equal
    anymore.
    
    (insn 62 60 63 4 (set (reg:DI 17 a7 [orig:154 loop_len_54 ] [154])
            (umin:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
                (reg:DI 30 t5 [219]))) 442 {umindi3}
         (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
                (const_int 8 [0x8]))
            (nil)))
    (insn 63 62 65 4 (set (reg:DI 15 a5 [orig:175 _103 ] [175])
            (minus:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
                (reg:DI 17 a7 [orig:154 loop_len_54 ] [154]))) 11 {subdi3}
         (nil))
    (insn 65 63 66 4 (set (reg:DI 16 a6 [orig:153 loop_len_53 ] [153])
            (umin:DI (reg:DI 15 a5 [orig:175 _103 ] [175])
                (reg:DI 30 t5 [219]))) 442 {umindi3}
         (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:175 _103 ] [175])
                (const_int 8 [0x8]))
            (nil)))
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-vsetvl.cc (source_equal_p): Use pointer
            equality for REG_EQUAL.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: New test.
    
    (cherry picked from commit 2020bce38cf2e02cbd1097faa8f1fd6586364a7e)

Diff:
---
 gcc/config/riscv/riscv-vsetvl.cc                   |  6 +++++-
 .../rvv/autovec/partial/multiple_rgroup_zbb.c      | 23 ++++++++++++++++++++++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 3fa25a6404d..8466b5d019e 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -560,7 +560,11 @@ source_equal_p (insn_info *insn1, insn_info *insn2)
 
   rtx note1 = find_reg_equal_equiv_note (rinsn1);
   rtx note2 = find_reg_equal_equiv_note (rinsn2);
-  if (note1 && note2 && rtx_equal_p (note1, note2))
+  /* We could handle the case of similar-looking REG_EQUALs as well but
+     would need to verify that no insn in between modifies any of the source
+     operands.  */
+  if (note1 && note2 && rtx_equal_p (note1, note2)
+      && REG_NOTE_KIND (note1) == REG_EQUIV)
     return true;
   return false;
 }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c
new file mode 100644
index 00000000000..15178a2c848
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } *.
+/* { dg-options "-march=rv64gcv_zbb -mabi=lp64d -O2 --param riscv-autovec-preference=fixed-vlmax -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include <stdint-gcc.h>
+
+void __attribute__ ((noipa))
+test (uint16_t *__restrict f, uint32_t *__restrict d, uint64_t *__restrict e,
+      uint16_t x, uint16_t x2, uint16_t x3, uint16_t x4, uint32_t y,
+      uint32_t y2, uint64_t z, int n)
+{
+  for (int i = 0; i < n; ++i)
+    {
+      f[i * 4 + 0] = x;
+      f[i * 4 + 1] = x2;
+      f[i * 4 + 2] = x3;
+      f[i * 4 + 3] = x4;
+      d[i * 2 + 0] = y;
+      d[i * 2 + 1] = y2;
+      e[i] = z;
+    }
+}
+
+/* { dg-final { scan-assembler-times "vsetvli\tzero,\s*\[a-z0-9\]+,\s*e16,\s*m1,\s*ta,\s*ma" 4 } } */