[gcc r14-5729] RISC-V/testsuite: Add branched cases for generic integer cond adds

[gcc r14-5729] RISC-V/testsuite: Add branched cases for generic integer cond adds

[Maciej W. Rozycki]

https://gcc.gnu.org/g:bbfe2639e18cbaa431f82d69fb79f34562a60881

commit r14-5729-gbbfe2639e18cbaa431f82d69fb79f34562a60881
Author: Maciej W. Rozycki <macro@embecosm.com>
Date:   Wed Nov 22 01:18:29 2023 +0000

    RISC-V/testsuite: Add branched cases for generic integer cond adds
    
    Verify, for generic integer conditional-add operations, if-conversion
    *not* to trigger at the respective sufficiently low `-mbranch-cost='
    settings that make original branched code sequences cheaper than their
    branchless equivalents if-conversion would emit.  Cover all integer
    relational operations to make sure no corner case escapes.
    
            gcc/testsuite/
            * gcc.target/riscv/adddibeq.c: New test.
            * gcc.target/riscv/adddibge.c: New test.
            * gcc.target/riscv/adddibgeu.c: New test.
            * gcc.target/riscv/adddibgt.c: New test.
            * gcc.target/riscv/adddibgtu.c: New test.
            * gcc.target/riscv/adddible.c: New test.
            * gcc.target/riscv/adddibleu.c: New test.
            * gcc.target/riscv/adddiblt.c: New test.
            * gcc.target/riscv/adddibltu.c: New test.
            * gcc.target/riscv/adddibne.c: New test.
            * gcc.target/riscv/addsibeq.c: New test.
            * gcc.target/riscv/addsibge.c: New test.
            * gcc.target/riscv/addsibgeu.c: New test.
            * gcc.target/riscv/addsibgt.c: New test.
            * gcc.target/riscv/addsibgtu.c: New test.
            * gcc.target/riscv/addsible.c: New test.
            * gcc.target/riscv/addsibleu.c: New test.
            * gcc.target/riscv/addsiblt.c: New test.
            * gcc.target/riscv/addsibltu.c: New test.
            * gcc.target/riscv/addsibne.c: New test.

Diff:
---
 gcc/testsuite/gcc.target/riscv/adddibeq.c  | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/adddibge.c  | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/adddibgeu.c | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/adddibgt.c  | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/adddibgtu.c | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/adddible.c  | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/adddibleu.c | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/adddiblt.c  | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/adddibltu.c | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/adddibne.c  | 28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsibeq.c  | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsibge.c  | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsibgeu.c | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsibgt.c  | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsibgtu.c | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsible.c  | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsibleu.c | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsiblt.c  | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsibltu.c | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsibne.c  | 28 ++++++++++++++++++++++++++++
 20 files changed, 524 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/adddibeq.c b/gcc/testsuite/gcc.target/riscv/adddibeq.c
new file mode 100644
index 00000000000..624c56ef6ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddibeq.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddieq (int_t w, int_t x, int_t y, int_t z)
+{
+  return w == x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bne	a0,a1,.L2
+	add	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\ssub\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddibge.c b/gcc/testsuite/gcc.target/riscv/adddibge.c
new file mode 100644
index 00000000000..017b69f7eaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddibge.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddige (int_t w, int_t x, int_t y, int_t z)
+{
+  return w >= x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	blt	a0,a1,.L2
+	add	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddibgeu.c b/gcc/testsuite/gcc.target/riscv/adddibgeu.c
new file mode 100644
index 00000000000..ed17898ed26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddibgeu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddigeu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w >= x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bltu	a0,a1,.L2
+	add	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddibgt.c b/gcc/testsuite/gcc.target/riscv/adddibgt.c
new file mode 100644
index 00000000000..201852fc62b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddibgt.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddigt (int_t w, int_t x, int_t y, int_t z)
+{
+  return w > x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	ble	a0,a1,.L2
+	add	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddibgtu.c b/gcc/testsuite/gcc.target/riscv/adddibgtu.c
new file mode 100644
index 00000000000..60850c4e1a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddibgtu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddigtu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w > x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bleu	a0,a1,.L2
+	add	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddible.c b/gcc/testsuite/gcc.target/riscv/adddible.c
new file mode 100644
index 00000000000..5bed30cd015
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddible.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddile (int_t w, int_t x, int_t y, int_t z)
+{
+  return w <= x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bgt	a0,a1,.L2
+	add	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddibleu.c b/gcc/testsuite/gcc.target/riscv/adddibleu.c
new file mode 100644
index 00000000000..3d16d09b340
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddibleu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddileu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w <= x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bgtu	a0,a1,.L2
+	add	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddiblt.c b/gcc/testsuite/gcc.target/riscv/adddiblt.c
new file mode 100644
index 00000000000..8ab979ddfc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddiblt.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddilt (int_t w, int_t x, int_t y, int_t z)
+{
+  return w < x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bge	a0,a1,.L2
+	add	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddibltu.c b/gcc/testsuite/gcc.target/riscv/adddibltu.c
new file mode 100644
index 00000000000..858e70f18c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddibltu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddiltu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w < x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bgeu	a0,a1,.L2
+	add	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddibne.c b/gcc/testsuite/gcc.target/riscv/adddibne.c
new file mode 100644
index 00000000000..e5dfee58e00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddibne.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddine (int_t w, int_t x, int_t y, int_t z)
+{
+  return w != x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	beq	a0,a1,.L3
+	add	a0,a2,a3
+	ret
+.L3:
+	mv	a0,a2
+	ret
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\ssub\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsibeq.c b/gcc/testsuite/gcc.target/riscv/addsibeq.c
new file mode 100644
index 00000000000..c1e810d8fab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsibeq.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsieq (int_t w, int_t x, int_t y, int_t z)
+{
+  return w == x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bne	a0,a1,.L2
+	addw	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sub|subw)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsibge.c b/gcc/testsuite/gcc.target/riscv/addsibge.c
new file mode 100644
index 00000000000..3f67d161f77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsibge.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsige (int_t w, int_t x, int_t y, int_t z)
+{
+  return w >= x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	blt	a0,a1,.L2
+	add[w]	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsibgeu.c b/gcc/testsuite/gcc.target/riscv/addsibgeu.c
new file mode 100644
index 00000000000..b6df5312671
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsibgeu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsigeu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w >= x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bltu	a0,a1,.L2
+	add[w]	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsibgt.c b/gcc/testsuite/gcc.target/riscv/addsibgt.c
new file mode 100644
index 00000000000..86fcd6d1402
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsibgt.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsigt (int_t w, int_t x, int_t y, int_t z)
+{
+  return w > x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	ble	a0,a1,.L2
+	add[w]	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsibgtu.c b/gcc/testsuite/gcc.target/riscv/addsibgtu.c
new file mode 100644
index 00000000000..63ebe65aaa9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsibgtu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsigtu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w > x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bleu	a0,a1,.L2
+	add[w]	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsible.c b/gcc/testsuite/gcc.target/riscv/addsible.c
new file mode 100644
index 00000000000..164d9c0e63b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsible.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsile (int_t w, int_t x, int_t y, int_t z)
+{
+  return w <= x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bgt	a0,a1,.L2
+	add[w]	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsibleu.c b/gcc/testsuite/gcc.target/riscv/addsibleu.c
new file mode 100644
index 00000000000..b02170b4176
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsibleu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsileu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w <= x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bgtu	a0,a1,.L2
+	add[w]	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsiblt.c b/gcc/testsuite/gcc.target/riscv/addsiblt.c
new file mode 100644
index 00000000000..a7911fddd25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsiblt.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsilt (int_t w, int_t x, int_t y, int_t z)
+{
+  return w < x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bge	a0,a1,.L2
+	add[w]	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsibltu.c b/gcc/testsuite/gcc.target/riscv/addsibltu.c
new file mode 100644
index 00000000000..69ee2a5e042
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsibltu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsiltu (int_t w, int_t x, int_t y, int_t z)
+{
+  return w < x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	bgeu	a0,a1,.L2
+	add[w]	a2,a2,a3
+.L2:
+	mv	a0,a2
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsibne.c b/gcc/testsuite/gcc.target/riscv/addsibne.c
new file mode 100644
index 00000000000..929e05765a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsibne.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=3 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsine (int_t w, int_t x, int_t y, int_t z)
+{
+  return w != x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	beq	a0,a1,.L3
+	add[w]	a0,a2,a3
+	ret
+.L3:
+	mv	a0,a2
+	ret
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:sub|subw)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */