[gcc r14-5731] RISC-V: Only use SUBREG if applicable in `riscv_expand_float_scc'

[Maciej W. Rozycki <macro@gcc.gnu.org>]

https://gcc.gnu.org/g:7e126d8d0fbe5677070f02c32a1425849ce36298

commit r14-5731-g7e126d8d0fbe5677070f02c32a1425849ce36298
Author: Maciej W. Rozycki <macro@embecosm.com>
Date:   Wed Nov 22 01:18:29 2023 +0000

    RISC-V: Only use SUBREG if applicable in `riscv_expand_float_scc'
    
    A subsequent change to enable the processing of conditional moves on a
    floating-point condition by `riscv_expand_conditional_move' will cause
    `riscv_expand_float_scc' to be called for word-mode target RTX with RV64
    targets.  In that case an invalid insn such as:
    
    (insn 25 24 0 (set (reg:DI 141)
            (subreg:SI (reg:DI 143) 0)) -1
         (nil))
    
    would be produced, which would crash the compiler later on.  Since the
    output operand of the SET operation to be produced already has the same
    mode as the input operand does, just omit the use of SUBREG and assign
    directly.
    
            gcc/
            * config/riscv/riscv.cc (riscv_expand_float_scc): Suppress the
            use of SUBREG if the conditional-set target is word-mode.

Diff:
---
 gcc/config/riscv/riscv.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index df08e9c831a..14e54939291 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4100,7 +4100,9 @@ riscv_expand_float_scc (rtx target, enum rtx_code code, rtx op0, rtx op1)
   riscv_emit_float_compare (&code, &op0, &op1);
 
   rtx cmp = riscv_force_binary (word_mode, code, op0, op1);
-  riscv_emit_set (target, lowpart_subreg (SImode, cmp, word_mode));
+  if (GET_MODE (target) != word_mode)
+    cmp = lowpart_subreg (GET_MODE (target), cmp, word_mode);
+  riscv_emit_set (target, cmp);
 }
 
 /* Jump to LABEL if (CODE OP0 OP1) holds.  */