[gcc r14-5742] RISC-V/testsuite: Add branched cases for FP NE cond-add operation

[gcc r14-5742] RISC-V/testsuite: Add branched cases for FP NE cond-add operation

[Maciej W. Rozycki]

https://gcc.gnu.org/g:23207facbbe6da8659608b3d69544a608152a415

commit r14-5742-g23207facbbe6da8659608b3d69544a608152a415
Author: Maciej W. Rozycki <macro@embecosm.com>
Date:   Wed Nov 22 01:18:31 2023 +0000

    RISC-V/testsuite: Add branched cases for FP NE cond-add operation
    
    Verify, for the generic floating-point NE conditional-add operation,
    that if-conversion does *not* trigger at `-mbranch-cost=2' setting,
    which makes original branched code sequences cheaper than their
    branchless equivalents if-conversion would emit.
    
            gcc/testsuite/
            * gcc.target/riscv/adddibfne.c: New test.
            * gcc.target/riscv/addsibfne.c: New test.

Diff:
---
 gcc/testsuite/gcc.target/riscv/adddibfne.c | 26 ++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/addsibfne.c | 26 ++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/adddibfne.c b/gcc/testsuite/gcc.target/riscv/adddibfne.c
new file mode 100644
index 00000000000..73ade4dcdfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddibfne.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddifne (double w, double x, int_t y, int_t z)
+{
+  return w != x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	feq.d	a5,fa0,fa1
+	bne	a5,zero,.L2
+	add	a0,a0,a1
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsibfne.c b/gcc/testsuite/gcc.target/riscv/addsibfne.c
new file mode 100644
index 00000000000..94da0710a26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsibfne.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsifne (double w, double x, int_t y, int_t z)
+{
+  return w != x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+	feq.d	a5,fa0,fa1
+	bne	a5,zero,.L2
+	add[w]	a0,a0,a1
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */