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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add cases for integer SFB cond-move operations
@ 2023-11-22 5:09 Jeff Law
0 siblings, 0 replies; only message in thread
From: Jeff Law @ 2023-11-22 5:09 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f3a02d15a5f898929179d46a6d1d982af383182d
commit f3a02d15a5f898929179d46a6d1d982af383182d
Author: Maciej W. Rozycki <macro@embecosm.com>
Date: Wed Nov 22 01:18:23 2023 +0000
RISC-V/testsuite: Add cases for integer SFB cond-move operations
Verify, for short forward branch targets and the conditional-move
operations that already work as expected, that if-conversion triggers
via `noce_try_cmove' already at `-mbranch-cost=1' and that extraneous
instructions such as SNEZ, etc. are not present in output. Cover all
integer relational operations to make sure no corner case escapes.
gcc/testsuite/
* gcc.target/riscv/movdieq-sfb.c: New test.
* gcc.target/riscv/movdige-sfb.c: New test.
* gcc.target/riscv/movdigeu-sfb.c: New test.
* gcc.target/riscv/movdigt-sfb.c: New test.
* gcc.target/riscv/movdigtu-sfb.c: New test.
* gcc.target/riscv/movdile-sfb.c: New test.
* gcc.target/riscv/movdileu-sfb.c: New test.
* gcc.target/riscv/movdilt-sfb.c: New test.
* gcc.target/riscv/movdiltu-sfb.c: New test.
* gcc.target/riscv/movdine-sfb.c: New test.
* gcc.target/riscv/movsieq-sfb.c: New test.
* gcc.target/riscv/movsige-sfb.c: New test.
* gcc.target/riscv/movsigeu-sfb.c: New test.
* gcc.target/riscv/movsigt-sfb.c: New test.
* gcc.target/riscv/movsigtu-sfb.c: New test.
* gcc.target/riscv/movsile-sfb.c: New test.
* gcc.target/riscv/movsileu-sfb.c: New test.
* gcc.target/riscv/movsilt-sfb.c: New test.
* gcc.target/riscv/movsiltu-sfb.c: New test.
* gcc.target/riscv/movsine-sfb.c: New test.
(cherry picked from commit 932fe50a8ba980f9cd92b0dcc15485ca503df30a)
Diff:
---
gcc/testsuite/gcc.target/riscv/movdieq-sfb.c | 25 +++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdige-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdigeu-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdigt-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdigtu-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdile-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdileu-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdilt-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdiltu-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdine-sfb.c | 25 +++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsieq-sfb.c | 25 +++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsige-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsigeu-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsigt-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsigtu-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsile-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsileu-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsilt-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsiltu-sfb.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsine-sfb.c | 25 +++++++++++++++++++++++++
20 files changed, 516 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/movdieq-sfb.c b/gcc/testsuite/gcc.target/riscv/movdieq-sfb.c
new file mode 100644
index 00000000000..aed11b0fb60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdieq-sfb.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdieq (int_t w, int_t x, int_t y, int_t z)
+{
+ return w == x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bne a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdige-sfb.c b/gcc/testsuite/gcc.target/riscv/movdige-sfb.c
new file mode 100644
index 00000000000..bcbc2635392
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdige-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdige (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ blt a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdigeu-sfb.c b/gcc/testsuite/gcc.target/riscv/movdigeu-sfb.c
new file mode 100644
index 00000000000..fd5abf06571
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdigeu-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdigeu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bltu a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdigt-sfb.c b/gcc/testsuite/gcc.target/riscv/movdigt-sfb.c
new file mode 100644
index 00000000000..f3c41869efc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdigt-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdigt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w > x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ ble a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdigtu-sfb.c b/gcc/testsuite/gcc.target/riscv/movdigtu-sfb.c
new file mode 100644
index 00000000000..a7881070456
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdigtu-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdigtu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w > x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bleu a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdile-sfb.c b/gcc/testsuite/gcc.target/riscv/movdile-sfb.c
new file mode 100644
index 00000000000..37587641c20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdile-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdile (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bgt a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|bgt)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdileu-sfb.c b/gcc/testsuite/gcc.target/riscv/movdileu-sfb.c
new file mode 100644
index 00000000000..312b52cef7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdileu-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdileu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bgtu a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdilt-sfb.c b/gcc/testsuite/gcc.target/riscv/movdilt-sfb.c
new file mode 100644
index 00000000000..f37b35ba8fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdilt-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdilt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w < x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bge a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdiltu-sfb.c b/gcc/testsuite/gcc.target/riscv/movdiltu-sfb.c
new file mode 100644
index 00000000000..fa799dfb358
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdiltu-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdiltu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w < x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bgeu a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdine-sfb.c b/gcc/testsuite/gcc.target/riscv/movdine-sfb.c
new file mode 100644
index 00000000000..40aec9c6366
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdine-sfb.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdine (int_t w, int_t x, int_t y, int_t z)
+{
+ return w != x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ beq a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsieq-sfb.c b/gcc/testsuite/gcc.target/riscv/movsieq-sfb.c
new file mode 100644
index 00000000000..8525f6a24ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsieq-sfb.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsieq (int_t w, int_t x, int_t y, int_t z)
+{
+ return w == x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bne a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsige-sfb.c b/gcc/testsuite/gcc.target/riscv/movsige-sfb.c
new file mode 100644
index 00000000000..cc9f2b56f76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsige-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsige (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ blt a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsigeu-sfb.c b/gcc/testsuite/gcc.target/riscv/movsigeu-sfb.c
new file mode 100644
index 00000000000..20bbf513625
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsigeu-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsigeu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bltu a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsigt-sfb.c b/gcc/testsuite/gcc.target/riscv/movsigt-sfb.c
new file mode 100644
index 00000000000..c494292b61a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsigt-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsigt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w > x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ ble a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgt|ble)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsigtu-sfb.c b/gcc/testsuite/gcc.target/riscv/movsigtu-sfb.c
new file mode 100644
index 00000000000..bfe4a5b29c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsigtu-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsigtu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w > x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bleu a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsile-sfb.c b/gcc/testsuite/gcc.target/riscv/movsile-sfb.c
new file mode 100644
index 00000000000..82a699578f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsile-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsile (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bgt a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsileu-sfb.c b/gcc/testsuite/gcc.target/riscv/movsileu-sfb.c
new file mode 100644
index 00000000000..e8b7c45dd07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsileu-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsileu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bgtu a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsilt-sfb.c b/gcc/testsuite/gcc.target/riscv/movsilt-sfb.c
new file mode 100644
index 00000000000..822c7785808
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsilt-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsilt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w < x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bge a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsiltu-sfb.c b/gcc/testsuite/gcc.target/riscv/movsiltu-sfb.c
new file mode 100644
index 00000000000..5fd441c366d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsiltu-sfb.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsiltu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w < x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ bgeu a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsine-sfb.c b/gcc/testsuite/gcc.target/riscv/movsine-sfb.c
new file mode 100644
index 00000000000..f7ac7c243c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsine-sfb.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsine (int_t w, int_t x, int_t y, int_t z)
+{
+ return w != x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+ beq a0,a1,1f # movcc
+ mv a3,a2
+1:
+ mv a0,a3
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
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2023-11-22 5:09 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add cases for integer SFB cond-move operations Jeff Law
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