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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Simplify EQ vs NE selection in `riscv_expand_conditional_move'
@ 2023-11-22 5:09 Jeff Law
0 siblings, 0 replies; only message in thread
From: Jeff Law @ 2023-11-22 5:09 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:b903e827990807ab691c033c72a3aebd60fe075f
commit b903e827990807ab691c033c72a3aebd60fe075f
Author: Maciej W. Rozycki <macro@embecosm.com>
Date: Wed Nov 22 01:18:24 2023 +0000
RISC-V: Simplify EQ vs NE selection in `riscv_expand_conditional_move'
Just choose between EQ and NE at `gen_rtx_fmt_ee' invocation, removing
an extraneous variable only referred once and improving code clarity.
gcc/
* config/riscv/riscv.cc (riscv_expand_conditional_move): Remove
extraneous variable for EQ vs NE operation selection.
(cherry picked from commit 35bea66d367520e6f62fc723bca6bf9cb291e581)
Diff:
---
gcc/config/riscv/riscv.cc | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 7450989f35e..6a7ecdb627f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4052,10 +4052,12 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
we can then use an equality comparison against zero. */
if (!equality_operator (op, VOIDmode) || op1 != CONST0_RTX (mode))
{
- enum rtx_code new_code = NE;
bool *invert_ptr = nullptr;
bool invert = false;
+ /* If riscv_expand_int_scc inverts the condition, then it will
+ flip the value of INVERT. We need to know where so that
+ we can adjust it for our needs. */
if (code == LE || code == GE)
invert_ptr = &invert;
@@ -4072,13 +4074,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
else
return false;
- /* If riscv_expand_int_scc inverts the condition, then it will
- flip the value of INVERT. We need to know where so that
- we can adjust it for our needs. */
- if (invert)
- new_code = EQ;
-
- op = gen_rtx_fmt_ee (new_code, mode, tmp, const0_rtx);
+ op = gen_rtx_fmt_ee (invert ? EQ : NE, mode, tmp, const0_rtx);
/* We've generated a new comparison. Update the local variables. */
code = GET_CODE (op);
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2023-11-22 5:09 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Simplify EQ vs NE selection in `riscv_expand_conditional_move' Jeff Law
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