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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branched cases for FP cond-move operations
@ 2023-11-22 5:09 Jeff Law
0 siblings, 0 replies; only message in thread
From: Jeff Law @ 2023-11-22 5:09 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ba5f0fe3867e19ceaade0c623f2aa4ca43c4fa95
commit ba5f0fe3867e19ceaade0c623f2aa4ca43c4fa95
Author: Maciej W. Rozycki <macro@embecosm.com>
Date: Wed Nov 22 01:18:25 2023 +0000
RISC-V/testsuite: Add branched cases for FP cond-move operations
Verify, for Ventana and Zicond targets and the ordered floating-point
conditional-move operations that already work as expected, that
if-conversion does *not* trigger at `-mbranch-cost=2' setting, which
makes original branched code sequences cheaper than their branchless
equivalents if-conversion would emit. Cover all ordered floating-point
relational operations to make sure no corner case escapes.
gcc/testsuite/
* gcc.target/riscv/movdibfge-ventana.c: New test.
* gcc.target/riscv/movdibfge-zicond.c: New test.
* gcc.target/riscv/movdibfgt-ventana.c: New test.
* gcc.target/riscv/movdibfgt-zicond.c: New test.
* gcc.target/riscv/movdibfle-ventana.c: New test.
* gcc.target/riscv/movdibfle-zicond.c: New test.
* gcc.target/riscv/movdibflt-ventana.c: New test.
* gcc.target/riscv/movdibflt-zicond.c: New test.
* gcc.target/riscv/movdibfne-ventana.c: New test.
* gcc.target/riscv/movdibfne-zicond.c: New test.
* gcc.target/riscv/movsibfge-ventana.c: New test.
* gcc.target/riscv/movsibfge-zicond.c: New test.
* gcc.target/riscv/movsibfgt-ventana.c: New test.
* gcc.target/riscv/movsibfgt-zicond.c: New test.
* gcc.target/riscv/movsibfle-ventana.c: New test.
* gcc.target/riscv/movsibfle-zicond.c: New test.
* gcc.target/riscv/movsibflt-ventana.c: New test.
* gcc.target/riscv/movsibflt-zicond.c: New test.
* gcc.target/riscv/movsibfne-ventana.c: New test.
* gcc.target/riscv/movsibfne-zicond.c: New test.
(cherry picked from commit bc40013cd6074f506f488c4717871ebcb7bb9087)
Diff:
---
gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c | 29 +++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c | 29 +++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c | 30 ++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c | 30 ++++++++++++++++++++++
20 files changed, 598 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c
new file mode 100644
index 00000000000..b80f5c9bf2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibfge-ventana.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifge (double w, double x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ fge.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c
new file mode 100644
index 00000000000..ed72259fc60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibfge-zicond.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifge (double w, double x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ fge.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c
new file mode 100644
index 00000000000..fd392ecd83c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibfgt-ventana.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifgt (double w, double x, int_t y, int_t z)
+{
+ return w > x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ fgt.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c
new file mode 100644
index 00000000000..158ad9e3006
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibfgt-zicond.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifgt (double w, double x, int_t y, int_t z)
+{
+ return w > x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ fgt.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c
new file mode 100644
index 00000000000..bc9d719b1e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibfle-ventana.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifle (double w, double x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ fle.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c
new file mode 100644
index 00000000000..ac9f159a656
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibfle-zicond.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifle (double w, double x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ fle.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c
new file mode 100644
index 00000000000..3a2610745ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibflt-ventana.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdiflt (double w, double x, int_t y, int_t z)
+{
+ return w < x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ flt.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c
new file mode 100644
index 00000000000..a8e362b9bb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibflt-zicond.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdiflt (double w, double x, int_t y, int_t z)
+{
+ return w < x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ flt.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c
new file mode 100644
index 00000000000..634872ad252
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibfne-ventana.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifne (double w, double x, int_t y, int_t z)
+{
+ return w != x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ feq.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ bne a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c
new file mode 100644
index 00000000000..24db9fa80ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibfne-zicond.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifne (double w, double x, int_t y, int_t z)
+{
+ return w != x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ feq.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ bne a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c
new file mode 100644
index 00000000000..e285102c373
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibfge-ventana.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifge (double w, double x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ fge.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c
new file mode 100644
index 00000000000..f696b337131
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibfge-zicond.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifge (double w, double x, int_t y, int_t z)
+{
+ return w >= x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ fge.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c
new file mode 100644
index 00000000000..f26577b7c6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibfgt-ventana.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifgt (double w, double x, int_t y, int_t z)
+{
+ return w > x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ fgt.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c
new file mode 100644
index 00000000000..4d1de867587
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibfgt-zicond.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifgt (double w, double x, int_t y, int_t z)
+{
+ return w > x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ fgt.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c
new file mode 100644
index 00000000000..a52721ef5de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibfle-ventana.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifle (double w, double x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ fle.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c
new file mode 100644
index 00000000000..b22292f4f78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibfle-zicond.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifle (double w, double x, int_t y, int_t z)
+{
+ return w <= x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ fle.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c
new file mode 100644
index 00000000000..5c40cb66c4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibflt-ventana.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsiflt (double w, double x, int_t y, int_t z)
+{
+ return w < x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ flt.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c
new file mode 100644
index 00000000000..502a8e5f7d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibflt-zicond.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsiflt (double w, double x, int_t y, int_t z)
+{
+ return w < x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ flt.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ beq a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c
new file mode 100644
index 00000000000..0f52852d6e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibfne-ventana.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifne (double w, double x, int_t y, int_t z)
+{
+ return w != x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ feq.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ bne a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c
new file mode 100644
index 00000000000..5f8df56acbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibfne-zicond.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifne (double w, double x, int_t y, int_t z)
+{
+ return w != x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+ feq.d a4,fa0,fa1
+ mv a5,a0
+ mv a0,a1
+ bne a4,zero,.L2
+ mv a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
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2023-11-22 5:09 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branched cases for FP cond-move operations Jeff Law
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