[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Also invert the cond-move condition for GEU and LEU

[Jeff Law <law@gcc.gnu.org>]

https://gcc.gnu.org/g:5980521decee54709d81c58f9e507c02281adb2f

commit 5980521decee54709d81c58f9e507c02281adb2f
Author: Maciej W. Rozycki <macro@embecosm.com>
Date:   Wed Nov 22 01:18:25 2023 +0000

    RISC-V: Also invert the cond-move condition for GEU and LEU
    
    Update `riscv_expand_conditional_move' and handle the missing GEU and
    LEU operators there, avoiding an extraneous conditional set operation,
    such as with this output:
    
            sgtu    a0,a0,a1
            seqz    a1,a0
            czero.eqz       a3,a3,a1
            czero.nez       a1,a2,a1
            or      a0,a1,a3
    
    produced when optimizing for Zicond targets from:
    
    int
    movsigtu (int w, int x, int y, int z)
    {
      return w > x ? y : z;
    }
    
    These operators can be inverted producing optimal code such as this:
    
            sgtu    a1,a0,a1
            czero.nez       a3,a3,a1
            czero.eqz       a1,a2,a1
            or      a0,a1,a3
    
    which this change causes to happen.
    
            gcc/
            * config/riscv/riscv.cc (riscv_expand_conditional_move): Also
            invert the condition for GEU and LEU.
    
    (cherry picked from commit db9d825b212994e89dabc710c61944552eb1fe90)

Diff:
---
 gcc/config/riscv/riscv.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e5f09c024cc..c7de7720c39 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4171,7 +4171,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
 	  /* If riscv_expand_int_scc inverts the condition, then it will
 	     flip the value of INVERT.  We need to know where so that
 	     we can adjust it for our needs.  */
-	  if (code == LE || code == GE)
+	  if (code == LE || code == LEU || code == GE || code == GEU)
 	    invert_ptr = &invert;
 
 	  /* Emit an scc like instruction into a temporary