From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id D9FF83858C33; Wed, 22 Nov 2023 05:10:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D9FF83858C33 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1700629823; bh=luiCIrZIPghTBMByHjnK9UqDd/QYqnR2FRvvz/HKV2U=; h=From:To:Subject:Date:From; b=yJ/e5SORQGC1RPUG21DSCLlYT16enkr9e+/BsRh/I4V3sV2Xb4/3wypSBDvAgHTGT cp/jrjC2o27oTlUFI1O4qLKKcMC9Zhcq4EyW25gIy5CGgq+9h+5I8Y6af2Krj/eKwR IFan8gft4oPrxeYrKOaFuPf9EdyU9/pqSZcl7rsU= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branched cases for equality cond-move operations X-Act-Checkin: gcc X-Git-Author: Maciej W. Rozycki X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 8ef4a2f6362e61b7b0d7afe33674e0af157bdfcb X-Git-Newrev: 3cc340f1f7293f9434f79f3243d7481b35a462aa Message-Id: <20231122051023.D9FF83858C33@sourceware.org> Date: Wed, 22 Nov 2023 05:10:23 +0000 (GMT) List-Id: https://gcc.gnu.org/g:3cc340f1f7293f9434f79f3243d7481b35a462aa commit 3cc340f1f7293f9434f79f3243d7481b35a462aa Author: Maciej W. Rozycki Date: Wed Nov 22 01:18:26 2023 +0000 RISC-V/testsuite: Add branched cases for equality cond-move operations Verify, for Ventana and Zicond targets and the equality conditional-move operations, that if-conversion does *not* trigger at the respective sufficiently low `-mbranch-cost=' settings that make original branched code sequences cheaper than their branchless equivalents if-conversion would emit. gcc/testsuite/ * gcc.target/riscv/movdibeq-ventana.c: New test. * gcc.target/riscv/movdibeq-zicond.c: New test. * gcc.target/riscv/movdibne-ventana.c: New test. * gcc.target/riscv/movdibne-zicond.c: New test. * gcc.target/riscv/movsibeq-ventana.c: New test. * gcc.target/riscv/movsibeq-zicond.c: New test. * gcc.target/riscv/movsibne-ventana.c: New test. * gcc.target/riscv/movsibne-zicond.c: New test. (cherry picked from commit 5e884a894206735cf1909edfe8a1410ac411c392) Diff: --- gcc/testsuite/gcc.target/riscv/movdibeq-ventana.c | 28 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdibeq-zicond.c | 28 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdibne-ventana.c | 30 +++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdibne-zicond.c | 30 +++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsibeq-ventana.c | 28 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsibeq-zicond.c | 28 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsibne-ventana.c | 30 +++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsibne-zicond.c | 30 +++++++++++++++++++++++ 8 files changed, 232 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/movdibeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibeq-ventana.c new file mode 100644 index 00000000000..c48e57e4fb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibeq-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdieq (int_t w, int_t x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branched assembly like: + + bne a0,a1,.L2 + mv a3,a2 +.L2: + mv a0,a3 + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\ssub\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibeq-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibeq-zicond.c new file mode 100644 index 00000000000..6f6173172bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibeq-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdieq (int_t w, int_t x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branched assembly like: + + bne a0,a1,.L2 + mv a3,a2 +.L2: + mv a0,a3 + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\ssub\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibne-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibne-ventana.c new file mode 100644 index 00000000000..5752f14dd4c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibne-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdine (int_t w, int_t x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branched assembly like: + + beq a0,a1,.L3 + mv a0,a2 + ret +.L3: + mv a0,a3 + ret + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\ssub\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdibne-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibne-zicond.c new file mode 100644 index 00000000000..1c97a3c3f92 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdibne-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdine (int_t w, int_t x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branched assembly like: + + beq a0,a1,.L3 + mv a0,a2 + ret +.L3: + mv a0,a3 + ret + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\ssub\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibeq-ventana.c new file mode 100644 index 00000000000..f9f69c587a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibeq-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsieq (int_t w, int_t x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branched assembly like: + + bne a0,a1,.L2 + mv a3,a2 +.L2: + mv a0,a3 + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\ssub\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibeq-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibeq-zicond.c new file mode 100644 index 00000000000..d2cc9a0e3c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibeq-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsieq (int_t w, int_t x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branched assembly like: + + bne a0,a1,.L2 + mv a3,a2 +.L2: + mv a0,a3 + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\ssub\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibne-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibne-ventana.c new file mode 100644 index 00000000000..cc1961ae787 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibne-ventana.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsine (int_t w, int_t x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branched assembly like: + + beq a0,a1,.L3 + mv a0,a2 + ret +.L3: + mv a0,a3 + ret + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\ssub\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */ +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsibne-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibne-zicond.c new file mode 100644 index 00000000000..0bc2e26eb52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsibne-zicond.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsine (int_t w, int_t x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branched assembly like: + + beq a0,a1,.L3 + mv a0,a2 + ret +.L3: + mv a0,a3 + ret + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\ssub\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */ +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */