From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id EA9A73858C53; Wed, 22 Nov 2023 05:10:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EA9A73858C53 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1700629828; bh=UIvA1uE1Wn4A/76zQkxrCRqdIqMXhezDpy/fkM5Pziw=; h=From:To:Subject:Date:From; b=Z+9KJGZvFpQ4KZsf8B+rzqD4xG+WTBom3wnLsA6N/HwgFZbtdC4Ozn+QX41bu3oE9 vjntrmjR+rUxDDZjZeDBOeNMIlQgsPaChLpIa58Qyd8e771iN38Ws803eoNK+HjIJN Phn0WAvhyVQvNHLITN7FYKGLj6ToDBRouqtijYz0= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branchless cases for equality cond-move operations X-Act-Checkin: gcc X-Git-Author: Maciej W. Rozycki X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 3cc340f1f7293f9434f79f3243d7481b35a462aa X-Git-Newrev: ca320374e907efbf28fd13e179c253289bc474a2 Message-Id: <20231122051028.EA9A73858C53@sourceware.org> Date: Wed, 22 Nov 2023 05:10:28 +0000 (GMT) List-Id: https://gcc.gnu.org/g:ca320374e907efbf28fd13e179c253289bc474a2 commit ca320374e907efbf28fd13e179c253289bc474a2 Author: Maciej W. Rozycki Date: Wed Nov 22 01:18:26 2023 +0000 RISC-V/testsuite: Add branchless cases for equality cond-move operations Verify, for Ventana and Zicond targets and the equality conditional-move operations, that if-conversion triggers via `noce_try_cmove' at the respective sufficiently high `-mbranch-cost=' settings that make branchless code sequences produced by if-conversion cheaper than their original branched equivalents, and that extraneous instructions such as SNEZ, etc. are not present in output. gcc/testsuite/ * gcc.target/riscv/movdieq-ventana.c: New test. * gcc.target/riscv/movdieq-zicond.c: New test. * gcc.target/riscv/movdine-ventana.c: New test. * gcc.target/riscv/movdine-zicond.c: New test. * gcc.target/riscv/movsieq-ventana.c: New test. * gcc.target/riscv/movsieq-zicond.c: New test. * gcc.target/riscv/movsine-ventana.c: New test. * gcc.target/riscv/movsine-zicond.c: New test. (cherry picked from commit c47fb7d09ea7b152f48129fb73af1bb24d65fcc3) Diff: --- gcc/testsuite/gcc.target/riscv/movdieq-ventana.c | 28 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdieq-zicond.c | 28 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdine-ventana.c | 28 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movdine-zicond.c | 28 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsieq-ventana.c | 28 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsieq-zicond.c | 28 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsine-ventana.c | 28 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movsine-zicond.c | 28 ++++++++++++++++++++++++ 8 files changed, 224 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/movdieq-ventana.c b/gcc/testsuite/gcc.target/riscv/movdieq-ventana.c new file mode 100644 index 00000000000..bca40ce788f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdieq-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdieq (int_t w, int_t x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + sub a1,a0,a1 + vt.maskc a3,a3,a1 + vt.maskcn a1,a2,a1 + or a0,a1,a3 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdieq-zicond.c b/gcc/testsuite/gcc.target/riscv/movdieq-zicond.c new file mode 100644 index 00000000000..3222c8771b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdieq-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdieq (int_t w, int_t x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + sub a1,a0,a1 + czero.eqz a3,a3,a1 + czero.nez a1,a2,a1 + or a0,a1,a3 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdine-ventana.c b/gcc/testsuite/gcc.target/riscv/movdine-ventana.c new file mode 100644 index 00000000000..0713bac83e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdine-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdine (int_t w, int_t x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branchless assembly like: + + sub a1,a0,a1 + vt.maskcn a3,a3,a1 + vt.maskc a1,a2,a1 + or a0,a1,a3 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movdine-zicond.c b/gcc/testsuite/gcc.target/riscv/movdine-zicond.c new file mode 100644 index 00000000000..825003be636 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movdine-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +movdine (int_t w, int_t x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branchless assembly like: + + sub a1,a0,a1 + czero.nez a3,a3,a1 + czero.eqz a1,a2,a1 + or a0,a1,a3 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsieq-ventana.c b/gcc/testsuite/gcc.target/riscv/movsieq-ventana.c new file mode 100644 index 00000000000..65be52f354b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsieq-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsieq (int_t w, int_t x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + sub a1,a0,a1 + vt.maskc a3,a3,a1 + vt.maskcn a1,a2,a1 + or a0,a1,a3 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsieq-zicond.c b/gcc/testsuite/gcc.target/riscv/movsieq-zicond.c new file mode 100644 index 00000000000..afa14c3bd5b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsieq-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=4 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsieq (int_t w, int_t x, int_t y, int_t z) +{ + return w == x ? y : z; +} + +/* Expect branchless assembly like: + + sub a1,a0,a1 + czero.eqz a3,a3,a1 + czero.nez a1,a2,a1 + or a0,a1,a3 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsine-ventana.c b/gcc/testsuite/gcc.target/riscv/movsine-ventana.c new file mode 100644 index 00000000000..c9a2538e894 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsine-ventana.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsine (int_t w, int_t x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branchless assembly like: + + sub a1,a0,a1 + vt.maskcn a3,a3,a1 + vt.maskc a1,a2,a1 + or a0,a1,a3 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/movsine-zicond.c b/gcc/testsuite/gcc.target/riscv/movsine-zicond.c new file mode 100644 index 00000000000..326c32cecb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movsine-zicond.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +movsine (int_t w, int_t x, int_t y, int_t z) +{ + return w != x ? y : z; +} + +/* Expect branchless assembly like: + + sub a1,a0,a1 + czero.nez a3,a3,a1 + czero.eqz a1,a2,a1 + or a0,a1,a3 + */ + +/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */ +/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */ +/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ +/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */