[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Also accept constants for T-Head cond-move comparison operands

[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V: Also accept constants for T-Head cond-move comparison operands

[Jeff Law]

https://gcc.gnu.org/g:f64a94a66c53a1fb44977d6afe88eb1a83051565

commit f64a94a66c53a1fb44977d6afe88eb1a83051565
Author: Maciej W. Rozycki <macro@embecosm.com>
Date:   Wed Nov 22 01:18:27 2023 +0000

    RISC-V: Also accept constants for T-Head cond-move comparison operands
    
    There is no need for the requirement for conditional-move comparison
    operands to be stricter for T-Head targets than for other targets and
    limit them to registers only.  Constants will be reloaded if required
    just as with branches or other-target conditional-move operations and
    there is no extra overhead specific to the T-Head case.  This enables
    more opportunities for a branchless sequence to be produced.
    
            gcc/
            * config/riscv/riscv.cc (riscv_expand_conditional_move): Also
            accept constants for T-Head comparison operands.
    
    (cherry picked from commit eeb112542f9a93974ee17d582ba649c50af95c86)

Diff:
---
 gcc/config/riscv/riscv.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e418ccc9061..ac2e76f4bed 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4126,8 +4126,8 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
       && reg_or_0_operand (cons, mode)
       && reg_or_0_operand (alt, mode)
       && (GET_MODE (op) == mode || GET_MODE (op) == E_VOIDmode)
-      && GET_MODE (op0) == mode
-      && GET_MODE (op1) == mode
+      && (GET_MODE (op0) == mode || CONST_INT_P (op0))
+      && (GET_MODE (op1) == mode || CONST_INT_P (op1))
       && (code == EQ || code == NE))
     need_eq_ne_p = true;