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From: Jeff Law <law@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branchless cases for generic integer cond adds
Date: Wed, 22 Nov 2023 05:11:29 +0000 (GMT) [thread overview]
Message-ID: <20231122051129.D8ADE3858C35@sourceware.org> (raw)
https://gcc.gnu.org/g:4051719d872008a0e382782d59891c3f420fd8d2
commit 4051719d872008a0e382782d59891c3f420fd8d2
Author: Maciej W. Rozycki <macro@embecosm.com>
Date: Wed Nov 22 01:18:29 2023 +0000
RISC-V/testsuite: Add branchless cases for generic integer cond adds
Verify, for generic integer conditional-add operations, if-conversion
to trigger via `noce_try_addcc' at the respective sufficiently high
`-mbranch-cost=' settings that make branchless code sequences produced
by if-conversion cheaper than their original branched equivalents, and,
where applicable, that extraneous instructions such as SNEZ, etc. are
not present in output. Cover all integer relational operations to make
sure no corner case escapes.
The reason to XFAIL SImode tests for RV64 targets is the compiler thinks
it has to sign-extend addends, which causes if-conversion to give up.
gcc/testsuite/
* gcc.target/riscv/adddieq.c: New test.
* gcc.target/riscv/adddige.c: New test.
* gcc.target/riscv/adddigeu.c: New test.
* gcc.target/riscv/adddigt.c: New test.
* gcc.target/riscv/adddigtu.c: New test.
* gcc.target/riscv/adddile.c: New test.
* gcc.target/riscv/adddileu.c: New test.
* gcc.target/riscv/adddilt.c: New test.
* gcc.target/riscv/adddiltu.c: New test.
* gcc.target/riscv/adddine.c: New test.
* gcc.target/riscv/addsieq.c: New test.
* gcc.target/riscv/addsige.c: New test.
* gcc.target/riscv/addsigeu.c: New test.
* gcc.target/riscv/addsigt.c: New test.
* gcc.target/riscv/addsigtu.c: New test.
* gcc.target/riscv/addsile.c: New test.
* gcc.target/riscv/addsileu.c: New test.
* gcc.target/riscv/addsilt.c: New test.
* gcc.target/riscv/addsiltu.c: New test.
* gcc.target/riscv/addsine.c: New test.
(cherry picked from commit 5e6903ddd39e058b9a8304a77765529d64819966)
Diff:
---
gcc/testsuite/gcc.target/riscv/adddieq.c | 27 +++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/adddige.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/adddigeu.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/adddigt.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/adddigtu.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/adddile.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/adddileu.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/adddilt.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/adddiltu.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/adddine.c | 27 +++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/addsieq.c | 27 +++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/addsige.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/addsigeu.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/addsigt.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/addsigtu.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/addsile.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/addsileu.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/addsilt.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/addsiltu.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/addsine.c | 27 +++++++++++++++++++++++++++
20 files changed, 524 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/adddieq.c b/gcc/testsuite/gcc.target/riscv/adddieq.c
new file mode 100644
index 00000000000..6195bf5584b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddieq.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddieq (int_t w, int_t x, int_t y, int_t z)
+{
+ return w == x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sub a1,a0,a1
+ seqz a1,a1
+ neg a1,a1
+ and a1,a1,a3
+ add a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:seqz|snez)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddige.c b/gcc/testsuite/gcc.target/riscv/adddige.c
new file mode 100644
index 00000000000..85e42244f3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddige.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddige (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ slt a1,a0,a1
+ addi a1,a1,-1
+ and a1,a1,a3
+ add a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddigeu.c b/gcc/testsuite/gcc.target/riscv/adddigeu.c
new file mode 100644
index 00000000000..f96714b9fb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddigeu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddigeu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sltu a1,a0,a1
+ addi a1,a1,-1
+ and a1,a1,a3
+ add a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddigt.c b/gcc/testsuite/gcc.target/riscv/adddigt.c
new file mode 100644
index 00000000000..047cbd4483c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddigt.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddigt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w > x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sgt a1,a0,a1
+ neg a1,a1
+ and a1,a1,a3
+ add a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddigtu.c b/gcc/testsuite/gcc.target/riscv/adddigtu.c
new file mode 100644
index 00000000000..10126369aab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddigtu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddigtu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w > x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sgtu a1,a0,a1
+ neg a1,a1
+ and a1,a1,a3
+ add a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddile.c b/gcc/testsuite/gcc.target/riscv/adddile.c
new file mode 100644
index 00000000000..e69b1957ace
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddile.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddile (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sgt a1,a0,a1
+ addi a1,a1,-1
+ and a1,a1,a3
+ add a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddileu.c b/gcc/testsuite/gcc.target/riscv/adddileu.c
new file mode 100644
index 00000000000..1e3bbd80080
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddileu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddileu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sgtu a1,a0,a1
+ addi a1,a1,-1
+ and a1,a1,a3
+ add a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddilt.c b/gcc/testsuite/gcc.target/riscv/adddilt.c
new file mode 100644
index 00000000000..647263ad5b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddilt.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddilt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w < x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ slt a1,a0,a1
+ neg a1,a1
+ and a1,a1,a3
+ add a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddiltu.c b/gcc/testsuite/gcc.target/riscv/adddiltu.c
new file mode 100644
index 00000000000..4a511b4290e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddiltu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" } */
+
+typedef unsigned int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddiltu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w < x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sltu a1,a0,a1
+ neg a1,a1
+ and a1,a1,a3
+ add a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/adddine.c b/gcc/testsuite/gcc.target/riscv/adddine.c
new file mode 100644
index 00000000000..00ff8757a55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddine.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddine (int_t w, int_t x, int_t y, int_t z)
+{
+ return w != x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sub a1,a0,a1
+ snez a1,a1
+ neg a1,a1
+ and a1,a1,a3
+ add a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\ssub\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:seqz|snez)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsieq.c b/gcc/testsuite/gcc.target/riscv/addsieq.c
new file mode 100644
index 00000000000..c5797a76a12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsieq.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsieq (int_t w, int_t x, int_t y, int_t z)
+{
+ return w == x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sub[w] a1,a0,a1
+ seqz a1,a1
+ neg[w] a1,a1
+ and a1,a1,a3
+ add[w] a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:sub|subw)\\s" 1 { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:seqz|snez)\\s" 1 { xfail rv64 } } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" { xfail rv64 } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsige.c b/gcc/testsuite/gcc.target/riscv/addsige.c
new file mode 100644
index 00000000000..461f2ade23b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsige.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsige (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ slt a1,a0,a1
+ addi[w] a1,a1,-1
+ and a1,a1,a3
+ add[w] a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 { xfail rv64 } } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" { xfail rv64 } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsigeu.c b/gcc/testsuite/gcc.target/riscv/addsigeu.c
new file mode 100644
index 00000000000..3afcc3375f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsigeu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsigeu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w >= x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sltu a1,a0,a1
+ addi[w] a1,a1,-1
+ and a1,a1,a3
+ add[w] a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 { xfail rv64 } } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" { xfail rv64 } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsigt.c b/gcc/testsuite/gcc.target/riscv/addsigt.c
new file mode 100644
index 00000000000..247626af8cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsigt.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsigt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w > x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sgt a1,a0,a1
+ neg[w] a1,a1
+ and a1,a1,a3
+ add[w] a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 { xfail rv64 } } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" { xfail rv64 } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsigtu.c b/gcc/testsuite/gcc.target/riscv/addsigtu.c
new file mode 100644
index 00000000000..c6948b45dff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsigtu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsigtu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w > x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sgtu a1,a0,a1
+ neg[w] a1,a1
+ and a1,a1,a3
+ add[w] a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 { xfail rv64 } } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" { xfail rv64 } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsile.c b/gcc/testsuite/gcc.target/riscv/addsile.c
new file mode 100644
index 00000000000..50725211644
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsile.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsile (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sgt a1,a0,a1
+ addi[w] a1,a1,-1
+ and a1,a1,a3
+ add[w] a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 { xfail rv64 } } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" { xfail rv64 } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsileu.c b/gcc/testsuite/gcc.target/riscv/addsileu.c
new file mode 100644
index 00000000000..2758a9e576b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsileu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsileu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w <= x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sgtu a1,a0,a1
+ addi[w] a1,a1,-1
+ and a1,a1,a3
+ add[w] a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 { xfail rv64 } } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" { xfail rv64 } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsilt.c b/gcc/testsuite/gcc.target/riscv/addsilt.c
new file mode 100644
index 00000000000..bad08e78dbd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsilt.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsilt (int_t w, int_t x, int_t y, int_t z)
+{
+ return w < x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ slt a1,a0,a1
+ neg[w] a1,a1
+ and a1,a1,a3
+ add[w] a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgt|slt)\\s" 1 { xfail rv64 } } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bge|bgt|ble|blt)\\s" { xfail rv64 } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsiltu.c b/gcc/testsuite/gcc.target/riscv/addsiltu.c
new file mode 100644
index 00000000000..0cee92fafaf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsiltu.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef unsigned int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsiltu (int_t w, int_t x, int_t y, int_t z)
+{
+ return w < x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sltu a1,a0,a1
+ neg[w] a1,a1
+ and a1,a1,a3
+ add[w] a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:sgtu|sltu)\\s" 1 { xfail rv64 } } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:bgeu|bgtu|bleu|bltu)\\s" { xfail rv64 } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsine.c b/gcc/testsuite/gcc.target/riscv/addsine.c
new file mode 100644
index 00000000000..4d45b83c550
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsine.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsine (int_t w, int_t x, int_t y, int_t z)
+{
+ return w != x ? y + z : y;
+}
+
+/* Expect branchless assembly like:
+
+ sub[w] a1,a0,a1
+ snez a1,a1
+ neg[w] a1,a1
+ and a1,a1,a3
+ add[w] a0,a1,a2
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_addcc" 1 "ce1" { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:sub|subw)\\s" 1 { xfail rv64 } } } */
+/* { dg-final { scan-assembler-times "\\s(?:seqz|snez)\\s" 1 { xfail rv64 } } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" { xfail rv64 } } } */
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