[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branchless cases for generic FP cond moves

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From: Jeff Law <law@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branchless cases for generic FP cond moves
Date: Wed, 22 Nov 2023 05:12:00 +0000 (GMT)	[thread overview]
Message-ID: <20231122051200.525B13858C2D@sourceware.org> (raw)

https://gcc.gnu.org/g:986526caa0ce884130c50dce4f4c6243282be04b

commit 986526caa0ce884130c50dce4f4c6243282be04b
Author: Maciej W. Rozycki <macro@embecosm.com>
Date:   Wed Nov 22 01:18:30 2023 +0000

    RISC-V/testsuite: Add branchless cases for generic FP cond moves
    
    Verify, for generic floating-point conditional-move operations that have
    a corresponding conditional-set machine instruction, that if-conversion
    triggers (via `cond_move_convert_if_block', which doesn't report) at
    `-mbranch-cost=5' setting, which makes branchless code sequences emitted
    by if-conversion cheaper than their original branched equivalents, and
    that extraneous instructions such as SNEZ, etc. are not present in
    output.
    
            gcc/testsuite/
            * gcc.target/riscv/movdifge.c: New test.
            * gcc.target/riscv/movdifgt.c: New test.
            * gcc.target/riscv/movdifle.c: New test.
            * gcc.target/riscv/movdiflt.c: New test.
            * gcc.target/riscv/movdifne.c: New test.
            * gcc.target/riscv/movsifge.c: New test.
            * gcc.target/riscv/movsifgt.c: New test.
            * gcc.target/riscv/movsifle.c: New test.
            * gcc.target/riscv/movsiflt.c: New test.
            * gcc.target/riscv/movsifne.c: New test.
    
    (cherry picked from commit 9d02897e885e547ac7af11883717b1539154db61)

Diff:
---
 gcc/testsuite/gcc.target/riscv/movdifge.c | 28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdifgt.c | 28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdifle.c | 28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdiflt.c | 28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdifne.c | 28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsifge.c | 28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsifgt.c | 28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsifle.c | 28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsiflt.c | 28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsifne.c | 28 ++++++++++++++++++++++++++++
 10 files changed, 280 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/movdifge.c b/gcc/testsuite/gcc.target/riscv/movdifge.c
new file mode 100644
index 00000000000..3193aaeb38a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdifge.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifge (double w, double x, int_t y, int_t z)
+{
+  return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	fge.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a0,a5,a0
+	not	a5,a5
+	and	a5,a5,a1
+	or	a0,a0,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdifgt.c b/gcc/testsuite/gcc.target/riscv/movdifgt.c
new file mode 100644
index 00000000000..466b4ab9a4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdifgt.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifgt (double w, double x, int_t y, int_t z)
+{
+  return w > x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	fgt.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a0,a5,a0
+	not	a5,a5
+	and	a5,a5,a1
+	or	a0,a0,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdifle.c b/gcc/testsuite/gcc.target/riscv/movdifle.c
new file mode 100644
index 00000000000..579f14dcb21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdifle.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifle (double w, double x, int_t y, int_t z)
+{
+  return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	fle.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a0,a5,a0
+	not	a5,a5
+	and	a5,a5,a1
+	or	a0,a0,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdiflt.c b/gcc/testsuite/gcc.target/riscv/movdiflt.c
new file mode 100644
index 00000000000..280eaa46f3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdiflt.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdiflt (double w, double x, int_t y, int_t z)
+{
+  return w < x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	flt.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a0,a5,a0
+	not	a5,a5
+	and	a5,a5,a1
+	or	a0,a0,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdifne.c b/gcc/testsuite/gcc.target/riscv/movdifne.c
new file mode 100644
index 00000000000..e06bb14ba0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdifne.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifne (double w, double x, int_t y, int_t z)
+{
+  return w != x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a1,a5,a1
+	not	a5,a5
+	and	a0,a5,a0
+	or	a0,a1,a0
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsifge.c b/gcc/testsuite/gcc.target/riscv/movsifge.c
new file mode 100644
index 00000000000..c3f170e5f13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsifge.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifge (double w, double x, int_t y, int_t z)
+{
+  return w >= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	fge.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a0,a5,a0
+	not	a5,a5
+	and	a5,a5,a1
+	or	a0,a0,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsifgt.c b/gcc/testsuite/gcc.target/riscv/movsifgt.c
new file mode 100644
index 00000000000..68aca07062d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsifgt.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifgt (double w, double x, int_t y, int_t z)
+{
+  return w > x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	fgt.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a0,a5,a0
+	not	a5,a5
+	and	a5,a5,a1
+	or	a0,a0,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsifle.c b/gcc/testsuite/gcc.target/riscv/movsifle.c
new file mode 100644
index 00000000000..3b1b06cf089
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsifle.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifle (double w, double x, int_t y, int_t z)
+{
+  return w <= x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	fle.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a0,a5,a0
+	not	a5,a5
+	and	a5,a5,a1
+	or	a0,a0,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fle\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsiflt.c b/gcc/testsuite/gcc.target/riscv/movsiflt.c
new file mode 100644
index 00000000000..a74d85978f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsiflt.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsiflt (double w, double x, int_t y, int_t z)
+{
+  return w < x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	flt.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a0,a5,a0
+	not	a5,a5
+	and	a5,a5,a1
+	or	a0,a0,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\s(?:fgt\\.d|flt\\.d)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsifne.c b/gcc/testsuite/gcc.target/riscv/movsifne.c
new file mode 100644
index 00000000000..f73f6f8c988
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsifne.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifne (double w, double x, int_t y, int_t z)
+{
+  return w != x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a1,a5,a1
+	not	a5,a5
+	and	a0,a5,a0
+	or	a0,a1,a0
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */

                 reply	other threads:[~2023-11-22  5:12 UTC|newest]

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