From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id 73EEE3858D35; Wed, 22 Nov 2023 05:12:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 73EEE3858D35 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1700629925; bh=Cr2n8VhpvOxdJUXDs+hamEd7ZBqXFHo0A+0YyB1ZjlY=; h=From:To:Subject:Date:From; b=ocLLJL0gpWbx5k2i4mV8LqSEUohoX2Xbbu/LeuUx54/4tQ+Bcs8sude0tkJiiiuFe BJut7fYVpHxQva8qFwDZBly89b8EV84XzGHfI1X9yAR7PBy5GaFZLVdsgTdNWVd7wU 7QC4SOEAPBafEG1GAyI2CTVir3YlgKvn5k83o4MA= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branched cases for generic FP cond adds X-Act-Checkin: gcc X-Git-Author: Maciej W. Rozycki X-Git-Refname: refs/vendors/riscv/heads/gcc-13-with-riscv-opts X-Git-Oldrev: 986526caa0ce884130c50dce4f4c6243282be04b X-Git-Newrev: 838562c01328cdff290e78bd3288546c27dec432 Message-Id: <20231122051205.73EEE3858D35@sourceware.org> Date: Wed, 22 Nov 2023 05:12:05 +0000 (GMT) List-Id: https://gcc.gnu.org/g:838562c01328cdff290e78bd3288546c27dec432 commit 838562c01328cdff290e78bd3288546c27dec432 Author: Maciej W. Rozycki Date: Wed Nov 22 01:18:30 2023 +0000 RISC-V/testsuite: Add branched cases for generic FP cond adds Verify, for generic floating-point conditional-add operations that have a corresponding conditional-set machine instruction, that if-conversion does *not* trigger at `-mbranch-cost=2' setting, which makes original branched code sequences cheaper than their branchless equivalents if-conversion would emit. Cover all the relevant floating-point relational operations to make sure no corner case escapes. gcc/testsuite/ * gcc.target/riscv/adddibfeq.c: New test. * gcc.target/riscv/adddibfge.c: New test. * gcc.target/riscv/adddibfgt.c: New test. * gcc.target/riscv/adddibfle.c: New test. * gcc.target/riscv/adddibflt.c: New test. * gcc.target/riscv/addsibfeq.c: New test. * gcc.target/riscv/addsibfge.c: New test. * gcc.target/riscv/addsibfgt.c: New test. * gcc.target/riscv/addsibfle.c: New test. * gcc.target/riscv/addsibflt.c: New test. (cherry picked from commit 2278c6443aa6aaa12b3682afb8ad0774575ae1b4) Diff: --- gcc/testsuite/gcc.target/riscv/adddibfeq.c | 26 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/adddibfge.c | 26 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/adddibfgt.c | 26 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/adddibfle.c | 26 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/adddibflt.c | 26 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/addsibfeq.c | 26 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/addsibfge.c | 26 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/addsibfgt.c | 26 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/addsibfle.c | 26 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/addsibflt.c | 26 ++++++++++++++++++++++++++ 10 files changed, 260 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/adddibfeq.c b/gcc/testsuite/gcc.target/riscv/adddibfeq.c new file mode 100644 index 00000000000..403200fd425 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/adddibfeq.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +adddifeq (double w, double x, int_t y, int_t z) +{ + return w == x ? y + z : y; +} + +/* Expect branched assembly like: + + feq.d a5,fa0,fa1 + beq a5,zero,.L2 + add a0,a0,a1 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/adddibfge.c b/gcc/testsuite/gcc.target/riscv/adddibfge.c new file mode 100644 index 00000000000..82fce9c58b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/adddibfge.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -ffinite-math-only -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +adddifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y + z : y; +} + +/* Expect branched assembly like: + + fge.d a5,fa0,fa1 + beq a5,zero,.L2 + add a0,a0,a1 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/adddibfgt.c b/gcc/testsuite/gcc.target/riscv/adddibfgt.c new file mode 100644 index 00000000000..0263154212d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/adddibfgt.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -ffinite-math-only -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +adddifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y + z : y; +} + +/* Expect branched assembly like: + + fgt.d a5,fa0,fa1 + beq a5,zero,.L2 + add a0,a0,a1 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/adddibfle.c b/gcc/testsuite/gcc.target/riscv/adddibfle.c new file mode 100644 index 00000000000..6fd65f1b470 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/adddibfle.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -ffinite-math-only -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +adddifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y + z : y; +} + +/* Expect branched assembly like: + + fle.d a5,fa0,fa1 + beq a5,zero,.L2 + add a0,a0,a1 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/adddibflt.c b/gcc/testsuite/gcc.target/riscv/adddibflt.c new file mode 100644 index 00000000000..bfee522a5cf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/adddibflt.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -ffinite-math-only -fdump-rtl-ce1" } */ + +typedef int __attribute__ ((mode (DI))) int_t; + +int_t +adddiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y + z : y; +} + +/* Expect branched assembly like: + + flt.d a5,fa0,fa1 + beq a5,zero,.L2 + add a0,a0,a1 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/addsibfeq.c b/gcc/testsuite/gcc.target/riscv/addsibfeq.c new file mode 100644 index 00000000000..27d13a0b4d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/addsibfeq.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +addsifeq (double w, double x, int_t y, int_t z) +{ + return w == x ? y + z : y; +} + +/* Expect branched assembly like: + + feq.d a5,fa0,fa1 + beq a5,zero,.L2 + add[w] a0,a0,a1 +.L2: + */ + +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/addsibfge.c b/gcc/testsuite/gcc.target/riscv/addsibfge.c new file mode 100644 index 00000000000..501f7562e66 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/addsibfge.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv64 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +addsifge (double w, double x, int_t y, int_t z) +{ + return w >= x ? y + z : y; +} + +/* Expect branched assembly like: + + fge.d a5,fa0,fa1 + beq a5,zero,.L2 + add[w] a0,a0,a1 +.L2: + */ + +/* { /* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/addsibfgt.c b/gcc/testsuite/gcc.target/riscv/addsibfgt.c new file mode 100644 index 00000000000..fff809b2b1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/addsibfgt.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv64 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +addsifgt (double w, double x, int_t y, int_t z) +{ + return w > x ? y + z : y; +} + +/* Expect branched assembly like: + + fgt.d a5,fa0,fa1 + beq a5,zero,.L2 + add[w] a0,a0,a1 +.L2: + */ + +/* { /* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/addsibfle.c b/gcc/testsuite/gcc.target/riscv/addsibfle.c new file mode 100644 index 00000000000..abcad61c9c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/addsibfle.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv64 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +addsifle (double w, double x, int_t y, int_t z) +{ + return w <= x ? y + z : y; +} + +/* Expect branched assembly like: + + fle.d a5,fa0,fa1 + beq a5,zero,.L2 + addw a0,a0,a1 +.L2: + */ + +/* { /* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/addsibflt.c b/gcc/testsuite/gcc.target/riscv/addsibflt.c new file mode 100644 index 00000000000..2a82c289e64 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/addsibflt.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ +/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -ffinite-math-only -fdump-rtl-ce1" { target { rv64 } } } */ + +typedef int __attribute__ ((mode (SI))) int_t; + +int_t +addsiflt (double w, double x, int_t y, int_t z) +{ + return w < x ? y + z : y; +} + +/* Expect branched assembly like: + + flt.d a5,fa0,fa1 + beq a5,zero,.L2 + addw a0,a0,a1 +.L2: + */ + +/* { /* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */ +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */ +/* { dg-final { scan-assembler-times "\\s(?:fge\\.d|fgt\\.d|fle\\.d|flt\\.d)\\s" 1 } } */ +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */ +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */