[gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branched cases for FP NE cond-move operations

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* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branched cases for FP NE cond-move operations
@ 2023-11-22  5:12 Jeff Law
  0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-11-22  5:12 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:3548f0a9f3e5c617d0a23947389fecdca3dd9a4d

commit 3548f0a9f3e5c617d0a23947389fecdca3dd9a4d
Author: Maciej W. Rozycki <macro@embecosm.com>
Date:   Wed Nov 22 01:18:31 2023 +0000

    RISC-V/testsuite: Add branched cases for FP NE cond-move operations
    
    Verify, for the floating-point NE conditional-move operation, that
    if-conversion triggers via `noce_try_cmove' at the respective
    sufficiently high `-mbranch-cost=' settings that make branchless code
    sequences produced by if-conversion cheaper than their original branched
    equivalents, and that extraneous instructions such as SNEZ, etc. are not
    present in output.
    
            gcc/testsuite/
            * gcc.target/riscv/movdifeq-sfb.c: New test.
            * gcc.target/riscv/movdifeq-thead.c: New test.
            * gcc.target/riscv/movdifeq-ventana.c: New test.
            * gcc.target/riscv/movdifeq-zicond.c: New test.
            * gcc.target/riscv/movdifeq.c: New test.
            * gcc.target/riscv/movsifeq-sfb.c: New test.
            * gcc.target/riscv/movsifeq-thead.c: New test.
            * gcc.target/riscv/movsifeq-ventana.c: New test.
            * gcc.target/riscv/movsifeq-zicond.c: New test.
            * gcc.target/riscv/movsifeq.c: New test.
    
    (cherry picked from commit f96e5fdeb65f841f99ef763f0e53a680106a8760)

Diff:
---
 gcc/testsuite/gcc.target/riscv/movdifeq-sfb.c     | 27 ++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdifeq-thead.c   | 25 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdifeq-ventana.c | 28 +++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdifeq-zicond.c  | 28 +++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdifeq.c         | 28 +++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsifeq-sfb.c     | 27 ++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsifeq-thead.c   | 25 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsifeq-ventana.c | 28 +++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsifeq-zicond.c  | 28 +++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsifeq.c         | 28 +++++++++++++++++++++++
 10 files changed, 272 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/movdifeq-sfb.c b/gcc/testsuite/gcc.target/riscv/movdifeq-sfb.c
new file mode 100644
index 00000000000..fe5a79a520a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdifeq-sfb.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+	feq.d	a5,fa0,fa1
+	beq	a5,zero,1f	# movcc
+	mv	a1,a0
+1:
+	mv	a0,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdifeq-thead.c b/gcc/testsuite/gcc.target/riscv/movdifeq-thead.c
new file mode 100644
index 00000000000..487e3eb7493
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdifeq-thead.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	th.mveqz	a0,a1,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdifeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movdifeq-ventana.c
new file mode 100644
index 00000000000..6d6c8019703
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdifeq-ventana.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	vt.maskcn	a1,a1,a5
+	vt.maskc	a0,a0,a5
+	or	a0,a0,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdifeq-zicond.c b/gcc/testsuite/gcc.target/riscv/movdifeq-zicond.c
new file mode 100644
index 00000000000..15bd6e13d7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdifeq-zicond.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	czero.nez	a1,a1,a5
+	czero.eqz	a0,a0,a5
+	or	a0,a0,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdifeq.c b/gcc/testsuite/gcc.target/riscv/movdifeq.c
new file mode 100644
index 00000000000..de6e17e5f80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdifeq.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a0,a5,a0
+	not	a5,a5
+	and	a5,a5,a1
+	or	a0,a0,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsifeq-sfb.c b/gcc/testsuite/gcc.target/riscv/movsifeq-sfb.c
new file mode 100644
index 00000000000..1f20bb4f45c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsifeq-sfb.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect short forward branch assembly like:
+
+	feq.d	a5,fa0,fa1
+	beq	a5,zero,1f	# movcc
+	mv	a1,a0
+1:
+	mv	a0,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s\[^\\s\]+\\s# movcc\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsifeq-thead.c b/gcc/testsuite/gcc.target/riscv/movsifeq-thead.c
new file mode 100644
index 00000000000..e2e69e00845
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsifeq-thead.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	th.mveqz	a0,a1,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:th\\.mveqz|th\\.mvnez)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsifeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movsifeq-ventana.c
new file mode 100644
index 00000000000..9fb29aa5bf4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsifeq-ventana.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	vt.maskcn	a1,a1,a5
+	vt.maskc	a0,a0,a5
+	or	a0,a0,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskc\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\svt\\.maskcn\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsifeq-zicond.c b/gcc/testsuite/gcc.target/riscv/movsifeq-zicond.c
new file mode 100644
index 00000000000..d967d328d83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsifeq-zicond.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	czero.nez	a1,a1,a5
+	czero.eqz	a0,a0,a5
+	or	a0,a0,a1
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.eqz\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\sczero\\.nez\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsifeq.c b/gcc/testsuite/gcc.target/riscv/movsifeq.c
new file mode 100644
index 00000000000..a4c0c674765
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsifeq.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=5 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branchless assembly like:
+
+	feq.d	a5,fa0,fa1
+	neg	a5,a5
+	and	a0,a5,a0
+	not	a5,a5
+	and	a5,a5,a1
+	or	a0,a0,a5
+ */
+
+/* { dg-final { scan-rtl-dump-times "Conversion succeeded on pass 1\\." 1 "ce1" } } */
+/* { dg-final { scan-rtl-dump-times "if-conversion succeeded through noce_try_cmove" 1 "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:beq|bne)\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */

^ permalink raw reply	[flat|nested] 2+ messages in thread

* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branched cases for FP NE cond-move operations
@ 2023-11-22  5:12 Jeff Law
  0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-11-22  5:12 UTC (permalink / raw)
  To: gcc-cvs

https://gcc.gnu.org/g:8ad28791ad66d0f5e4974a99cf9fbe8c337c058b

commit 8ad28791ad66d0f5e4974a99cf9fbe8c337c058b
Author: Maciej W. Rozycki <macro@embecosm.com>
Date:   Wed Nov 22 01:18:31 2023 +0000

    RISC-V/testsuite: Add branched cases for FP NE cond-move operations
    
    Verify, for generic, Ventana and Zicond targets and the floating-point
    NE conditional-move operation, that if-conversion does *not* trigger at
    the respective sufficiently low `-mbranch-cost=' settings that make
    original branched code sequences cheaper than their branchless
    equivalents if-conversion would emit.
    
            gcc/testsuite/
            * gcc.target/riscv/movdibfeq-ventana.c: New test.
            * gcc.target/riscv/movdibfeq-zicond.c: New test.
            * gcc.target/riscv/movdibfeq.c: New test.
            * gcc.target/riscv/movsibfeq-ventana.c: New test.
            * gcc.target/riscv/movsibfeq-zicond.c: New test.
            * gcc.target/riscv/movsibfeq.c: New test.
    
    (cherry picked from commit 4c69b5fbb98343ccd9a9f18069847b195b4b7cc7)

Diff:
---
 gcc/testsuite/gcc.target/riscv/movdibfeq-ventana.c | 30 ++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdibfeq-zicond.c  | 30 ++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movdibfeq.c         | 28 ++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsibfeq-ventana.c | 30 ++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsibfeq-zicond.c  | 30 ++++++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/movsibfeq.c         | 28 ++++++++++++++++++++
 6 files changed, 176 insertions(+)

diff --git a/gcc/testsuite/gcc.target/riscv/movdibfeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movdibfeq-ventana.c
new file mode 100644
index 00000000000..e43b642a58c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibfeq-ventana.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	feq.d	a4,fa0,fa1
+	mv	a5,a0
+	mv	a0,a1
+	beq	a4,zero,.L2
+	mv	a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibfeq-zicond.c b/gcc/testsuite/gcc.target/riscv/movdibfeq-zicond.c
new file mode 100644
index 00000000000..ea4ff149696
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibfeq-zicond.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	feq.d	a4,fa0,fa1
+	mv	a5,a0
+	mv	a0,a1
+	beq	a4,zero,.L2
+	mv	a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movdibfeq.c b/gcc/testsuite/gcc.target/riscv/movdibfeq.c
new file mode 100644
index 00000000000..03c934beff8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movdibfeq.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+movdifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	feq.d	a4,fa0,fa1
+	mv	a5,a0
+	mv	a0,a1
+	beq	a4,zero,.L2
+	mv	a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibfeq-ventana.c b/gcc/testsuite/gcc.target/riscv/movsibfeq-ventana.c
new file mode 100644
index 00000000000..44ecadc08f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibfeq-ventana.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	feq.d	a4,fa0,fa1
+	mv	a5,a0
+	mv	a0,a1
+	beq	a4,zero,.L2
+	mv	a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
+/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibfeq-zicond.c b/gcc/testsuite/gcc.target/riscv/movsibfeq-zicond.c
new file mode 100644
index 00000000000..addbb2ed279
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibfeq-zicond.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=2 -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	feq.d	a4,fa0,fa1
+	mv	a5,a0
+	mv	a0,a1
+	beq	a4,zero,.L2
+	mv	a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
+/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/movsibfeq.c b/gcc/testsuite/gcc.target/riscv/movsibfeq.c
new file mode 100644
index 00000000000..27b101415dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/movsibfeq.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=4 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+movsifeq (double w, double x, int_t y, int_t z)
+{
+  return w == x ? y : z;
+}
+
+/* Expect branched assembly like:
+
+	feq.d	a4,fa0,fa1
+	mv	a5,a0
+	mv	a0,a1
+	beq	a4,zero,.L2
+	mv	a0,a5
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2023-11-22  5:12 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branched cases for FP NE cond-move operations Jeff Law
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2023-11-22  5:12 Jeff Law

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