public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branched cases for FP NE cond-add operation
@ 2023-11-22 5:12 Jeff Law
0 siblings, 0 replies; only message in thread
From: Jeff Law @ 2023-11-22 5:12 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:bc5a9139cfef0387eacc2bb626d60bf6962a4f1e
commit bc5a9139cfef0387eacc2bb626d60bf6962a4f1e
Author: Maciej W. Rozycki <macro@embecosm.com>
Date: Wed Nov 22 01:18:31 2023 +0000
RISC-V/testsuite: Add branched cases for FP NE cond-add operation
Verify, for the generic floating-point NE conditional-add operation,
that if-conversion does *not* trigger at `-mbranch-cost=2' setting,
which makes original branched code sequences cheaper than their
branchless equivalents if-conversion would emit.
gcc/testsuite/
* gcc.target/riscv/adddibfne.c: New test.
* gcc.target/riscv/addsibfne.c: New test.
(cherry picked from commit 23207facbbe6da8659608b3d69544a608152a415)
Diff:
---
gcc/testsuite/gcc.target/riscv/adddibfne.c | 26 ++++++++++++++++++++++++++
gcc/testsuite/gcc.target/riscv/addsibfne.c | 26 ++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/adddibfne.c b/gcc/testsuite/gcc.target/riscv/adddibfne.c
new file mode 100644
index 00000000000..73ade4dcdfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/adddibfne.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target rv64 } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" } */
+
+typedef int __attribute__ ((mode (DI))) int_t;
+
+int_t
+adddifne (double w, double x, int_t y, int_t z)
+{
+ return w != x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+ feq.d a5,fa0,fa1
+ bne a5,zero,.L2
+ add a0,a0,a1
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/addsibfne.c b/gcc/testsuite/gcc.target/riscv/addsibfne.c
new file mode 100644
index 00000000000..94da0710a26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/addsibfne.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+/* { dg-options "-march=rv32gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc -mtune=sifive-5-series -mbranch-cost=2 -mmovcc -fdump-rtl-ce1" { target { rv64 } } } */
+
+typedef int __attribute__ ((mode (SI))) int_t;
+
+int_t
+addsifne (double w, double x, int_t y, int_t z)
+{
+ return w != x ? y + z : y;
+}
+
+/* Expect branched assembly like:
+
+ feq.d a5,fa0,fa1
+ bne a5,zero,.L2
+ add[w] a0,a0,a1
+.L2:
+ */
+
+/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
+/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
+/* { dg-final { scan-assembler-times "\\sfeq\\.d\\s" 1 } } */
+/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
+/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2023-11-22 5:12 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-11-22 5:12 [gcc(refs/vendors/riscv/heads/gcc-13-with-riscv-opts)] RISC-V/testsuite: Add branched cases for FP NE cond-add operation Jeff Law
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).