From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 20323385841A; Thu, 23 Nov 2023 12:10:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 20323385841A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1700741453; bh=+vfwtcZPLrQb3S6l4daDXe4c+BqPF12VeVOZgQgNles=; h=From:To:Subject:Date:From; b=ZyFBtqN7DAZ9rbgayn5qFjH9e7zNLbwYWFW2qKgCLzYc7jiNXFpfV4NZjuYBRxzl5 GTwr4Af0kdV6vrzbBYHZKWnyedgL0awEYZCAXTHiuf2P4mGp2UQNJo8z4pqw+Ngsli e82X9v4wk046U7m1msBZIoXvcAOaAlEpoUgUHfJo= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-5778] RISC-V: Add wrapper for emit vec_extract[NFC] X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 35a688f434159a923420310860c5bc721e29a741 X-Git-Newrev: ef296fb37cac12a5a10e83c16ae021a624e1238c Message-Id: <20231123121053.20323385841A@sourceware.org> Date: Thu, 23 Nov 2023 12:10:53 +0000 (GMT) List-Id: https://gcc.gnu.org/g:ef296fb37cac12a5a10e83c16ae021a624e1238c commit r14-5778-gef296fb37cac12a5a10e83c16ae021a624e1238c Author: Juzhe-Zhong Date: Thu Nov 23 20:07:35 2023 +0800 RISC-V: Add wrapper for emit vec_extract[NFC] Add wrapper for vec_extract since my following patch will need to call it. gcc/ChangeLog: * config/riscv/riscv-protos.h (emit_vec_extract): New function. * config/riscv/riscv-v.cc (emit_vec_extract): Ditto. * config/riscv/riscv.cc (riscv_legitimize_move): Refine codes. Diff: --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 22 ++++++++++++++++++++++ gcc/config/riscv/riscv.cc | 12 +----------- 3 files changed, 24 insertions(+), 11 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 52097fe48cf..c74c2e94a4f 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -558,6 +558,7 @@ void expand_cond_binop (unsigned, rtx *); void expand_cond_ternop (unsigned, rtx *); void expand_popcount (rtx *); void expand_rawmemchr (machine_mode, rtx, rtx, rtx); +void emit_vec_extract (rtx, rtx, poly_int64); /* Rounding mode bitfield for fixed point VXRM. */ enum fixed_point_rounding_mode diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 24b09c0dd2d..72b96d8339d 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4636,4 +4636,26 @@ can_be_broadcasted_p (rtx op) return can_create_pseudo_p () && nonmemory_operand (op, mode); } +/* Helper function to emit vec_extract_optab. */ +void +emit_vec_extract (rtx target, rtx src, poly_int64 index) +{ + machine_mode vmode = GET_MODE (src); + machine_mode smode = GET_MODE (target); + class expand_operand ops[3]; + enum insn_code icode + = convert_optab_handler (vec_extract_optab, vmode, smode); + gcc_assert (icode != CODE_FOR_nothing); + create_output_operand (&ops[0], target, smode); + ops[0].target = 1; + create_input_operand (&ops[1], src, vmode); + if (index.is_constant ()) + create_integer_operand (&ops[2], index); + else + create_input_operand (&ops[2], gen_int_mode (index, Pmode), Pmode); + expand_insn (icode, 3, ops); + if (ops[0].value != target) + emit_move_insn (target, ops[0].value); +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d0efb939bf2..425463ebb18 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2616,14 +2616,10 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) nunits = nunits * 2; } vmode = riscv_vector::get_vector_mode (smode, nunits).require (); - enum insn_code icode - = convert_optab_handler (vec_extract_optab, vmode, smode); - gcc_assert (icode != CODE_FOR_nothing); rtx v = gen_lowpart (vmode, SUBREG_REG (src)); for (unsigned int i = 0; i < num; i++) { - class expand_operand ops[3]; rtx result; if (num == 1) result = dest; @@ -2631,13 +2627,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) result = gen_lowpart (smode, dest); else result = gen_reg_rtx (smode); - create_output_operand (&ops[0], result, smode); - ops[0].target = 1; - create_input_operand (&ops[1], v, vmode); - create_integer_operand (&ops[2], index + i); - expand_insn (icode, 3, ops); - if (ops[0].value != result) - emit_move_insn (result, ops[0].value); + riscv_vector::emit_vec_extract (result, v, index + i); if (i == 1) {