[gcc r14-5840] aarch64: Fix up aarch64_simd_stp<mode> [PR109977]

[gcc r14-5840] aarch64: Fix up aarch64_simd_stp<mode> [PR109977]

[Jakub Jelinek]

https://gcc.gnu.org/g:a6a43a3b763816fec7c4eec6ae7be5b263dff340

commit r14-5840-ga6a43a3b763816fec7c4eec6ae7be5b263dff340
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat Nov 25 10:30:39 2023 +0100

    aarch64: Fix up aarch64_simd_stp<mode> [PR109977]
    
    The aarch64_simd_stp<mode> pattern uses w constraint in one alternative and
    r in another, but for the latter incorrectly uses <vw> iterator in %<vw>1 which
    expands to %d1 for V2DF and %s1 for V2SF and V4SF (this one not relevant to
    the pattern) and %w1 for others, so it ICEs if the alternative is selected
    during final.  Compared to this, <vwcore> macro has the same values for all
    modes but uses w for V2DF and V2SF.
    
    2023-11-24  Andrew Pinski  <pinskia@gmail.com>
                Jakub Jelinek  <jakub@redhat.com>
    
            PR target/109977
            * config/aarch64/aarch64-simd.md (aarch64_simd_stp<mode>): Use <vwcore>
            rather than %<vw> for alternative with r constraint on input operand.
    
            * gcc.dg/pr109977.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64-simd.md |  2 +-
 gcc/testsuite/gcc.dg/pr109977.c    | 16 ++++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 80e338bb895..ad79a8110a5 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -269,7 +269,7 @@
   "TARGET_SIMD"
   {@ [ cons: =0 , 1 ; attrs: type            ]
      [ Umn      , w ; neon_stp               ] stp\t%<Vetype>1, %<Vetype>1, %y0
-     [ Umn      , r ; store_<ldpstp_vel_sz>  ] stp\t%<vw>1, %<vw>1, %y0
+     [ Umn      , r ; store_<ldpstp_vel_sz>  ] stp\t%<vwcore>1, %<vwcore>1, %y0
   }
 )
 
diff --git a/gcc/testsuite/gcc.dg/pr109977.c b/gcc/testsuite/gcc.dg/pr109977.c
new file mode 100644
index 00000000000..03d9a333134
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr109977.c
@@ -0,0 +1,16 @@
+/* PR target/109977 */
+/* { dg-do compile } */
+/* { dg-options "-Og" } */
+
+typedef double __attribute__((__vector_size__ (8))) V;
+typedef double __attribute__((__vector_size__ (16))) W;
+V v;
+int i;
+extern void bar (void *);
+
+void
+foo (void)
+{
+  W w = __builtin_shufflevector (v, (W) { }, 0, 0);
+  bar (&w);
+}