From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id EBDFD3858C2A; Tue, 12 Dec 2023 02:09:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EBDFD3858C2A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1702346993; bh=/oedFA8cGp8qdK68qQ/4HvzhBg3NxxtY9tCj/s31OG8=; h=From:To:Subject:Date:From; b=DolavJwm+hvhcVgRnicapwQRizUICJ9j0Egb00Xf2xAKWyqfJnfogaPYLR2tALyY+ +u7ZydFypG9AlW/aLZoPXjAd2AW5SOrNxfvsWpZdioa+TtbaIbbkmWsiUMuGWmds+9 Q1MrNJvB4Sp8UMjbgGV0wqBC20z+ryNFDp0gRyJs= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-6441] RISC-V: Move RVV POLY VALUE estimation from riscv.cc to riscv-v.cc[NFC] X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 4b421728289e6f1caa0dfaa953a11698ab95d37d X-Git-Newrev: fda2e1ab60377ca1a6aff093355b29115cff5880 Message-Id: <20231212020953.EBDFD3858C2A@sourceware.org> Date: Tue, 12 Dec 2023 02:09:53 +0000 (GMT) List-Id: https://gcc.gnu.org/g:fda2e1ab60377ca1a6aff093355b29115cff5880 commit r14-6441-gfda2e1ab60377ca1a6aff093355b29115cff5880 Author: Juzhe-Zhong Date: Tue Dec 12 10:06:38 2023 +0800 RISC-V: Move RVV POLY VALUE estimation from riscv.cc to riscv-v.cc[NFC] This patch moves RVV POLY VALUE estimation from riscv.cc to riscv-v.cc for future better maintain like other target hook implementation. Committed as it is obviously a code refinement. gcc/ChangeLog: * config/riscv/riscv-protos.h (estimated_poly_value): New function. * config/riscv/riscv-v.cc (estimated_poly_value): Ditto. * config/riscv/riscv.cc (riscv_estimated_poly_value): Move RVV POLY VALUE estimation to riscv-v.cc Diff: --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 47 +++++++++++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv.cc | 44 ++++---------------------------------- 3 files changed, 52 insertions(+), 40 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 20bbb5b859c..85ab1db2088 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -608,6 +608,7 @@ int count_regno_occurrences (rtx_insn *, unsigned int); bool imm_avl_p (machine_mode); bool can_be_broadcasted_p (rtx); bool gather_scatter_valid_offset_p (machine_mode); +HOST_WIDE_INT estimated_poly_value (poly_int64, unsigned int); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 944b37b5df7..01898cb4b8d 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4927,4 +4927,51 @@ gather_scatter_valid_offset_p (machine_mode mode) return true; } +/* Implement TARGET_ESTIMATED_POLY_VALUE. + Look into the tuning structure for an estimate. + KIND specifies the type of requested estimate: min, max or likely. + For cores with a known VLA width all three estimates are the same. + For generic VLA tuning we want to distinguish the maximum estimate from + the minimum and likely ones. + The likely estimate is the same as the minimum in that case to give a + conservative behavior of auto-vectorizing with VLA when it is a win + even for VLA vectorization. + When VLA width information is available VAL.coeffs[1] is multiplied by + the number of VLA chunks over the initial VLS bits. */ +HOST_WIDE_INT +estimated_poly_value (poly_int64 val, unsigned int kind) +{ + unsigned int width_source + = BITS_PER_RISCV_VECTOR.is_constant () + ? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant () + : (unsigned int) RVV_SCALABLE; + + /* If there is no core-specific information then the minimum and likely + values are based on TARGET_MIN_VLEN vectors and the maximum is based on + the architectural maximum of 65536 bits. */ + unsigned int min_vlen_bytes = TARGET_MIN_VLEN / 8 - 1; + if (width_source == RVV_SCALABLE) + switch (kind) + { + case POLY_VALUE_MIN: + case POLY_VALUE_LIKELY: + return val.coeffs[0]; + + case POLY_VALUE_MAX: + return val.coeffs[0] + val.coeffs[1] * min_vlen_bytes; + } + + /* Allow BITS_PER_RISCV_VECTOR to be a bitmask of different VL, treating the + lowest as likely. This could be made more general if future -mtune + options need it to be. */ + if (kind == POLY_VALUE_MAX) + width_source = 1 << floor_log2 (width_source); + else + width_source = least_bit_hwi (width_source); + + /* If the core provides width information, use that. */ + HOST_WIDE_INT over_min_vlen = width_source - TARGET_MIN_VLEN; + return val.coeffs[0] + val.coeffs[1] * over_min_vlen / TARGET_MIN_VLEN; +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 3f111fa0393..69a8a503f30 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -9604,51 +9604,15 @@ riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor, return RISCV_DWARF_VLENB; } -/* Implement TARGET_ESTIMATED_POLY_VALUE. - Look into the tuning structure for an estimate. - KIND specifies the type of requested estimate: min, max or likely. - For cores with a known RVV width all three estimates are the same. - For generic RVV tuning we want to distinguish the maximum estimate from - the minimum and likely ones. - The likely estimate is the same as the minimum in that case to give a - conservative behavior of auto-vectorizing with RVV when it is a win - even for 128-bit RVV. - When RVV width information is available VAL.coeffs[1] is multiplied by - the number of VQ chunks over the initial Advanced SIMD 128 bits. */ +/* Implement TARGET_ESTIMATED_POLY_VALUE. */ static HOST_WIDE_INT riscv_estimated_poly_value (poly_int64 val, poly_value_estimate_kind kind = POLY_VALUE_LIKELY) { - unsigned int width_source = BITS_PER_RISCV_VECTOR.is_constant () - ? (unsigned int) BITS_PER_RISCV_VECTOR.to_constant () - : (unsigned int) RVV_SCALABLE; - - /* If there is no core-specific information then the minimum and likely - values are based on 128-bit vectors and the maximum is based on - the architectural maximum of 65536 bits. */ - if (width_source == RVV_SCALABLE) - switch (kind) - { - case POLY_VALUE_MIN: - case POLY_VALUE_LIKELY: - return val.coeffs[0]; - - case POLY_VALUE_MAX: - return val.coeffs[0] + val.coeffs[1] * 15; - } - - /* Allow BITS_PER_RISCV_VECTOR to be a bitmask of different VL, treating the - lowest as likely. This could be made more general if future -mtune - options need it to be. */ - if (kind == POLY_VALUE_MAX) - width_source = 1 << floor_log2 (width_source); - else - width_source = least_bit_hwi (width_source); - - /* If the core provides width information, use that. */ - HOST_WIDE_INT over_128 = width_source - 128; - return val.coeffs[0] + val.coeffs[1] * over_128 / 128; + if (TARGET_VECTOR) + return riscv_vector::estimated_poly_value (val, kind); + return default_estimated_poly_value (val, kind); } /* Return true if the vector misalignment factor is supported by the