From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 30CE0385828B; Wed, 17 Jan 2024 09:03:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 30CE0385828B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1705482182; bh=lwtV+jpoOny8H0t4nv2eu5daZqpyo+1BOuIS9gcikjg=; h=From:To:Subject:Date:From; b=Vix5zzn/sKgH2SVTeflIBRUsizB+aLLMPhDiZhsI1WcBHAe2VgFL4L8fW14czRrx0 OUvwv9G+dkE7sx8Sngtn6wv2AdhmXP4Y0IoxeCEjWDfuMhbGDhkTkSox8fgJsrNypj Utmg/2a12RN9VOkGHs2t7TVSAtECTe5TKOB6ti7o= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-8176] RISC-V: Fix asm checks regression due to recent middle-end change X-Act-Checkin: gcc X-Git-Author: Pan Li X-Git-Refname: refs/heads/master X-Git-Oldrev: 3359942417b02de88ae84d50aac232ac01ff9e15 X-Git-Newrev: de4c9a27ba51e409e9d9e2a2827da53b1c979b09 Message-Id: <20240117090302.30CE0385828B@sourceware.org> Date: Wed, 17 Jan 2024 09:03:02 +0000 (GMT) List-Id: https://gcc.gnu.org/g:de4c9a27ba51e409e9d9e2a2827da53b1c979b09 commit r14-8176-gde4c9a27ba51e409e9d9e2a2827da53b1c979b09 Author: Pan Li Date: Wed Jan 17 16:56:56 2024 +0800 RISC-V: Fix asm checks regression due to recent middle-end change The recent middle-end change result in some asm check failures. This patch would like to fix the asm check by adjust the times. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/shift-1.c: Fix asm check count. * gcc.target/riscv/rvv/autovec/vls/shift-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/shift-3.c: Ditto. Signed-off-by: Pan Li Diff: --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c index e57a0b6bdf3..cb5a1dbc9ff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c @@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, int64_t, >>) DEF_OP_VV (shift, 256, int64_t, >>) DEF_OP_VV (shift, 512, int64_t, >>) -/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 39 } } */ +/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c index 9d1fa64232c..e626a52c2d8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c @@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, uint64_t, >>) DEF_OP_VV (shift, 256, uint64_t, >>) DEF_OP_VV (shift, 512, uint64_t, >>) -/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 39 } } */ +/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c index 8de1b9c0c41..244bee02e55 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c @@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, int64_t, <<) DEF_OP_VV (shift, 256, int64_t, <<) DEF_OP_VV (shift, 512, int64_t, <<) -/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 46 } } */ +/* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 47 } } */ /* { dg-final { scan-assembler-not {csrr} } } */