From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7924) id 375703858C2F; Mon, 22 Jan 2024 07:01:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 375703858C2F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1705906886; bh=IPiwGE7cnpTBofg3U4tcH6BRvpNPoS9wJRQfux0sImM=; h=From:To:Subject:Date:From; b=k5vqJj5XM91UJOr5VsGHqaMoa059tFhvr8cipAQA74LWQPuZYmkRXIn1wobcCeafX UeLonDpy8yEyHNW0PR/bKPYoUH5mTkuz+f2b1GHl6JNAc/kR2ZMdcX15VR9ki6Td2P k1lKc5GTN6TjpuKNUuj/iLJu2GSEnf1glkuR0GEo= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Pan Li To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-8329] RISC-V: Fix vfirst/vmsbf/vmsif/vmsof ratio attributes X-Act-Checkin: gcc X-Git-Author: Juzhe-Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 46a664dd59ec6c1121914d6857d6edb94501c517 X-Git-Newrev: a618b3c65745a6992ced4df60c186241c2da6eae Message-Id: <20240122070126.375703858C2F@sourceware.org> Date: Mon, 22 Jan 2024 07:01:25 +0000 (GMT) List-Id: https://gcc.gnu.org/g:a618b3c65745a6992ced4df60c186241c2da6eae commit r14-8329-ga618b3c65745a6992ced4df60c186241c2da6eae Author: Juzhe-Zhong Date: Mon Jan 22 10:49:05 2024 +0800 RISC-V: Fix vfirst/vmsbf/vmsif/vmsof ratio attributes vfirst/vmsbf/vmsif/vmsof instructions are supposed to demand ratio instead of demanding sew_lmul. But my previous typo makes VSETVL PASS miss honor the risc-v v spec. Consider this following simple case: int foo4 (void * in, void * out) { vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); v = __riscv_vadd_vv_i32m1 (v, v, 4); vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32(v); mask = __riscv_vmsof_m_b32(mask, 4); return __riscv_vfirst_m_b32(mask, 4); } Before this patch: foo4: vsetivli zero,4,e32,m1,ta,ma vle32.v v1,0(a0) vadd.vv v1,v1,v1 vsetvli zero,zero,e8,mf4,ta,ma ----> redundant. vmsof.m v2,v1 vfirst.m a0,v2 ret After this patch: foo4: vsetivli zero,4,e32,m1,ta,ma vle32.v v1,0(a0) vadd.vv v1,v1,v1 vmsof.m v2,v1 vfirst.m a0,v2 ret Confirm RVV spec and Clang, this patch makes VSETVL PASS match the correct behavior. Tested on both RV32/RV64, no regression. gcc/ChangeLog: * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/attribute-1.c: New test. Diff: --- gcc/config/riscv/vector.md | 2 +- .../gcc.target/riscv/rvv/vsetvl/attribute-1.c | 47 ++++++++++++++++++++++ 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index cfc54ae5eac..307d9a8c952 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -433,7 +433,7 @@ vialu,vshift,vicmp,vimul,vidiv,vsalu,\ vext,viwalu,viwmul,vicalu,vnshift,\ vimuladd,vimerge,vaalu,vsmul,vsshift,\ - vnclip,viminmax,viwmuladd,vmffs,vmsfs,\ + vnclip,viminmax,viwmuladd,\ vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,\ vfwalu,vfwmul,vfsqrt,vfrecp,vfsgnj,vfcmp,\ vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c new file mode 100644 index 00000000000..28dcf986bac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/attribute-1.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +int +foo (void *in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + v = __riscv_vadd_vv_i32m1 (v, v, 4); + vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32 (v); + return __riscv_vfirst_m_b32 (mask, 4); +} + +int +foo2 (void *in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + v = __riscv_vadd_vv_i32m1 (v, v, 4); + vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32 (v); + mask = __riscv_vmsbf_m_b32 (mask, 4); + return __riscv_vfirst_m_b32 (mask, 4); +} + +int +foo3 (void *in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + v = __riscv_vadd_vv_i32m1 (v, v, 4); + vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32 (v); + mask = __riscv_vmsif_m_b32 (mask, 4); + return __riscv_vfirst_m_b32 (mask, 4); +} + +int +foo4 (void *in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + v = __riscv_vadd_vv_i32m1 (v, v, 4); + vbool32_t mask = __riscv_vreinterpret_v_i32m1_b32 (v); + mask = __riscv_vmsof_m_b32 (mask, 4); + return __riscv_vfirst_m_b32 (mask, 4); +} + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e32,\s*m1,\s*t[au],\s*m[au]} 4 } } */ +/* { dg-final { scan-assembler-times {vsetivli} 4 } } */ +/* { dg-final { scan-assembler-not {vsetvli} } } */