From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id C0DC03858D3C; Tue, 23 Jan 2024 07:38:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C0DC03858D3C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1705995481; bh=6DaCNmFBS+2MX8gnWdO04jh3E3d0Y06crMlSPgB8Sj0=; h=From:To:Subject:Date:From; b=FmpZ2S43GDb07OIYhqij0s77a7TiPmx0VQssxZsAUZ5q+iNysu2z6+qnpRCyv86UZ 5VZBCLkPydL7eseCjWPjQpCC4TQgo2Y26FKDf8fyGdYg2CM8jBTwJjtwNsPva/nNtA Sde+V+ARC45ygkaHTdAEztRQloFGxI/br5aeiUyA= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work154-vcombo)] Update ChangeLog.* X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work154-vcombo X-Git-Oldrev: ea987aafefb63acd3b6ee5a9c850d55a09be6f1d X-Git-Newrev: d8c123fa226b228c4425fc26d74830bfa377184c Message-Id: <20240123073801.C0DC03858D3C@sourceware.org> Date: Tue, 23 Jan 2024 07:38:01 +0000 (GMT) List-Id: https://gcc.gnu.org/g:d8c123fa226b228c4425fc26d74830bfa377184c commit d8c123fa226b228c4425fc26d74830bfa377184c Author: Michael Meissner Date: Tue Jan 23 02:37:58 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.vcombo | 288 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 287 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vcombo b/gcc/ChangeLog.vcombo index 979d9345d69..c993fe77474 100644 --- a/gcc/ChangeLog.vcombo +++ b/gcc/ChangeLog.vcombo @@ -1,6 +1,292 @@ +==================== Branch work154-vcombo, vsubreg154 patch #300 ==================== + +Peter's patches for subreg support. + +2024-01-23 Peter Bergner + +gcc/ + + PR target/109116 + * gcc/config/rs6000/rs6000.cc (rs6000_modes_tieable_p): Make OOmode + tieable with 128-bit vector modes. + +2024-01-23 Peter Bergner + +gcc/ + + PR target/109116 + * gcc/config/rs6000/mma.md (vsx_disassemble_pair): Use SUBREG's instead + of UNSPEC's. + (mma_disassemble_acc): Likewise. + +==================== Branch work154-vcombo, vpair patch #204 ==================== + +Add vector pair optimizations. + +2024-01-23 Michael Meissner + +gcc/ + + * config/rs6000/vector-pair.md (vpair_add_neg_3): New + combiner insn to convert vector plus/neg into a minus operation. + (vpair_fma__merge): Optimize multiply, add/subtract, and + negation into fma operations if the user specifies to create fmas. + (vpair_fma__merge): Likewise. + (vpair_fma__merge2): Likewise. + (vpair_nfma__merge): Likewise. + (vpair_nfms__merge): Likewise. + (vpair_nfms__merge2): Likewise. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-pair-7.c: New test. + * gcc.target/powerpc/vector-pair-8.c: Likewise. + * gcc.target/powerpc/vector-pair-9.c: Likewise. + * gcc.target/powerpc/vector-pair-10.c: Likewise. + * gcc.target/powerpc/vector-pair-11.c: Likewise. + * gcc.target/powerpc/vector-pair-12xs.c: Likewise. + +==================== Branch work154-vcombo, vpair patch #204 ==================== + +Add vector pair init and splat. + +2024-01-23 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-builtins.def (__builtin_vpair_zero): New + built-in function. + (__builtin_vpair_f32_splat): Likewise. + (__builtin_vpair_f64_splat): Likewise. + * config/rs6000/vector-pair.md (UNSPEC_VPAIR_ZERO): New unspec. + (UNSPEC_VPAIR_SPLAT): Likewise. + (VPAIR_SPLAT_VMODE): New mode iterator. + (VPAIR_SPLAT_ELEMENT_TO_VMODE): New mode attribute. + (vpair_splat_name): Likewise. + (vpair_zero): New insn. + (vpair_splat_): New define_expand. + (vpair_splat__internal): New insns. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-pair-5.c: New test. + * gcc.target/powerpc/vector-pair-6.c: Likewise. + +==================== Branch work154-vcombo, vpair patch #204 ==================== + +Add support for vector pair fma operations. + +2024-01-23 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-builtins.def (__builtin_vpair_f32_fma): New + built-in. + (__builtin_vpair_f32_fms): Likewise. + (__builtin_vpair_f32_nfma): Likewise. + (__builtin_vpair_f32_nfms): Likewise. + (__builtin_vpair_f64_fma): Likewise. + (__builtin_vpair_f64_fms): Likewise. + (__builtin_vpair_f64_nfma): Likewise. + * config/rs6000/rs6000/rs6000-proto.h (enum vpair_split_fma): New + enumeration. + (vpair_split_fma): New declaration. + * config/rs6000/rs6000.cc (vpair_split_fma): New function to split + vector pair FMA operations. + * config/rs6000/vector-pair.md (UNSPEC_VPAIR_FMA): New unspec. + (vpair_stdname): Add UNSPEC_VPAIR_FMA. + (VPAIR_OP): Likewise. + (vpair_fma_4): New insns. + (vpair_fms_4): Likewise. + (vpair_nfma_4): Likewise. + (vpair_nfms_4): Likewise. + * doc/extend.texi (PowerPC Vector Pair Built-in Functions): Document new + vector pair fma built-in functions. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-pair-3.c: New test. + * gcc.target/powerpc/vector-pair-4.c: Likewise. + +==================== Branch work154-vcombo, vpair patch #204 ==================== + +Add support for vector pair unary and binary operations. + +2024-01-23 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-builtins.def (__builtin_vpair_*): Add new + built-in functions for vector pair support. + * config/rs6000/rs6000-protos.h (enum vpair_split_unary): New + enumeration. + (vpair_split_unary): New declaration. + (vpair_split_binary): Likewise. + * config/rs6000/rs6000.cc (vpair_split_unary): New function to split + vector pair operations. + (vpair_split_binary): Likewise. + * config/rs6000/rs6000.md (toplevel): Include vector-pair.md. + * config/rs6000/t-rs6000 (MD_INCLUDES): Add vector-pair.md. + * config/rs6000/vector-pair.md: New file. + * doc/extend.texi (PowerPC Vector Pair Built-in Functions): Add + documentation for the new vector pair built-in functions. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-pair-1.c: New test. + * gcc.target/powerpc/vector-pair-2.c: Likewise. + +==================== Branch work154-vcombo, work154 patch #2 ==================== + +PR target/112886, Add %S to print_operand for vector pair support. + +In looking at support for load vector pair and store vector pair for the +PowerPC in GCC, I noticed that we were missing a print_operand output modifier +if you are dealing with vector pairs to print the 2nd register in the vector +pair. + +If the instruction inside of the asm used the Altivec encoding, then we could +use the %L modifier: + + __vector_pair *p, *q, *r; + // ... + __asm__ ("vaddudm %0,%1,%2\n\tvaddudm %L0,%L1,%L2" + : "=v" (*p) + : "v" (*q), "v" (*r)); + +Likewise if we know the value to be in a tradiational FPR register, %L will +work for instructions that use the VSX encoding: + + __vector_pair *p, *q, *r; + // ... + __asm__ ("xvadddp %x0,%x1,%x2\n\txvadddp %L0,%L1,%L2" + : "=f" (*p) + : "f" (*q), "f" (*r)); + +But if have a value that is in a traditional Altivec register, and the +instruction uses the VSX encoding, %L will a value between 0 and 31, when it +should give a value between 32 and 63. + +This patch adds %S that acts like %x, except that it adds 1 to the +register number. + +I have tested this on power10 and power9 little endian systems and on a power9 +big endian system. There were no regressions in the patch. Can I apply it to +the trunk? + +It would be nice if I could apply it to the open branches. Can I backport it +after a burn-in period? + +2024-01-23 Michael Meissner + +gcc/ + + PR target/112886 + * config/rs6000/rs6000.cc (print_operand): Add %S output modifier. + * doc/md.texi (Modifiers): Mention %S can be used like %x. + +gcc/testsuite/ + + PR target/112886 + * /gcc.target/powerpc/pr112886.c: New test. + +==================== Branch work154-vcombo, work154 patch #1 ==================== + +Power10: Add options to disable load and store vector pair. + +This is version 2 of the patch to add -mno-load-vector-pair and +-mno-store-vector-pair undocumented tuning switches. + +The differences between the first version of the patch and this version is that +I added explicit RTL abi attributes for when the compiler can generate the load +vector pair and store vector pair instructions. By having this attribute, the +movoo insn has separate alternatives for when we generate the instruction and +when we want to split the instruction into 2 separate vector loads or stores. + +In the first version of the patch, I had previously provided built-in functions +that would always generate load vector pair and store vector pair instructions +even if these instructions are normally disabled. I found these built-ins +weren't specified like the other vector pair built-ins, and I didn't include +documentation for the built-in functions. If we want such built-in functions, +we can add them as a separate patch later. + +In addition, since both versions of the patch adds #pragma target and attribute +support to change the results for individual functions, we can select on a +function by function basis what the defaults for load/store vector pair is. + +The original text for the patch is: + +In working on some future patches that involve utilizing vector pair +instructions, I wanted to be able to tune my program to enable or disable using +the vector pair load or store operations while still keeping the other +operations on the vector pair. + +This patch adds two undocumented tuning options. The -mno-load-vector-pair +option would tell GCC to generate two load vector instructions instead of a +single load vector pair. The -mno-store-vector-pair option would tell GCC to +generate two store vector instructions instead of a single store vector pair. + +If either -mno-load-vector-pair is used, GCC will not generate the indexed +stxvpx instruction. Similarly if -mno-store-vector-pair is used, GCC will not +generate the indexed lxvpx instruction. The reason for this is to enable +splitting the {,p}lxvp or {,p}stxvp instructions after reload without needing a +scratch GPR register. + +The default for -mcpu=power10 is that both load vector pair and store vector +pair are enabled. + +I added code so that the user code can modify these settings using either a +'#pragma GCC target' directive or used __attribute__((__target__(...))) in the +function declaration. + +I added tests for the switches, #pragma, and attribute options. + +I have built this on both little endian power10 systems and big endian power9 +systems doing the normal bootstrap and test. There were no regressions in any +of the tests, and the new tests passed. Can I check this patch into the master +branch? + +2024-01-23 Michael Meissner + +gcc/ + + * config/rs6000/mma.md (movoo): Add support for -mno-load-vector-pair and + -mno-store-vector-pair. + * config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add support for + -mload-vector-pair and -mstore-vector-pair. + (POWERPC_MASKS): Likewise. + * config/rs6000/rs6000.cc (rs6000_setup_reg_addr_masks): Only allow + indexed mode for OOmode if we are generating both load vector pair and + store vector pair instructions. + (rs6000_option_override_internal): Add support for -mno-load-vector-pair + and -mno-store-vector-pair. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.md (isa attribute): Add lxvp and stxvp + attributes. + (enabled attribute): Likewise. + * config/rs6000/rs6000.opt (-mload-vector-pair): New option. + (-mstore-vector-pair): Likewise. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-pair-attribute.c: New test. + * gcc.target/powerpc/vector-pair-pragma.c: New test. + * gcc.target/powerpc/vector-pair-switch1.c: New test. + * gcc.target/powerpc/vector-pair-switch2.c: New test. + * gcc.target/powerpc/vector-pair-switch3.c: New test. + * gcc.target/powerpc/vector-pair-switch4.c: New test. + ==================== Branch work154-vcombo, baseline ==================== +Add ChangeLog.vcombo and update REVISION. + +2024-01-22 Michael Meissner + +gcc/ + + * ChangeLog.vcombo: New file for branch. + * REVISION: Update. + 2024-01-22 Michael Meissner Clone branch -