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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work154-acombo)] Update ChangeLog.* Date: Tue, 23 Jan 2024 07:48:07 +0000 (GMT) [thread overview] Message-ID: <20240123074808.1787B3858C50@sourceware.org> (raw) https://gcc.gnu.org/g:6d74798ede1fbbc159fe1f4b9ab7b1ca7090e00c commit 6d74798ede1fbbc159fe1f4b9ab7b1ca7090e00c Author: Michael Meissner <meissner@linux.ibm.com> Date: Tue Jan 23 02:48:05 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.acombo | 335 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 334 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.acombo b/gcc/ChangeLog.acombo index 2f7abb42436..8cda4db5506 100644 --- a/gcc/ChangeLog.acombo +++ b/gcc/ChangeLog.acombo @@ -1,6 +1,339 @@ +==================== Branch work154-acombo, work154-vsubreg patch #300 ==================== + +Peter's patches for subreg support. + +2024-01-23 Peter Bergner <bergner@linux.ibm.com> + +gcc/ + + PR target/109116 + * gcc/config/rs6000/rs6000.cc (rs6000_modes_tieable_p): Make OOmode + tieable with 128-bit vector modes. + +2024-01-23 Peter Bergner <bergner@linux.ibm.com> + +gcc/ + + PR target/109116 + * gcc/config/rs6000/mma.md (vsx_disassemble_pair): Use SUBREG's instead + of UNSPEC's. + (mma_disassemble_acc): Likewise. + +==================== Branch work154-acombo, work154-pair patch #204 ==================== + +Add vector pair optimizations. + +2024-01-23 Michael Meissner <meissner@linux.ibm.com> + +gcc/ + + * config/rs6000/vector-pair.md (vpair_add_neg_<vpair_modename>3): New + combiner insn to convert vector plus/neg into a minus operation. + (vpair_fma_<vpair_modename>_merge): Optimize multiply, add/subtract, and + negation into fma operations if the user specifies to create fmas. + (vpair_fma_<vpair_modename>_merge): Likewise. + (vpair_fma_<vpair_modename>_merge2): Likewise. + (vpair_nfma_<vpair_modename>_merge): Likewise. + (vpair_nfms_<vpair_modename>_merge): Likewise. + (vpair_nfms_<vpair_modename>_merge2): Likewise. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-pair-7.c: New test. + * gcc.target/powerpc/vector-pair-8.c: Likewise. + * gcc.target/powerpc/vector-pair-9.c: Likewise. + * gcc.target/powerpc/vector-pair-10.c: Likewise. + * gcc.target/powerpc/vector-pair-11.c: Likewise. + * gcc.target/powerpc/vector-pair-12xs.c: Likewise. + +==================== Branch work154-acombo, work154-pair patch #203 ==================== + +Add vector pair init and splat. + +2024-01-23 Michael Meissner <meissner@linux.ibm.com> + +gcc/ + + * config/rs6000/rs6000-builtins.def (__builtin_vpair_zero): New + built-in function. + (__builtin_vpair_f32_splat): Likewise. + (__builtin_vpair_f64_splat): Likewise. + * config/rs6000/vector-pair.md (UNSPEC_VPAIR_ZERO): New unspec. + (UNSPEC_VPAIR_SPLAT): Likewise. + (VPAIR_SPLAT_VMODE): New mode iterator. + (VPAIR_SPLAT_ELEMENT_TO_VMODE): New mode attribute. + (vpair_splat_name): Likewise. + (vpair_zero): New insn. + (vpair_splat_<vpair_splat_name>): New define_expand. + (vpair_splat_<vpair_splat_name>_internal): New insns. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-pair-5.c: New test. + * gcc.target/powerpc/vector-pair-6.c: Likewise. + +==================== Branch work154-acombo, work154-pair patch #202 ==================== + +Add support for vector pair fma operations. + +2024-01-23 Michael Meissner <meissner@linux.ibm.com> + +gcc/ + + * config/rs6000/rs6000-builtins.def (__builtin_vpair_f32_fma): New + built-in. + (__builtin_vpair_f32_fms): Likewise. + (__builtin_vpair_f32_nfma): Likewise. + (__builtin_vpair_f32_nfms): Likewise. + (__builtin_vpair_f64_fma): Likewise. + (__builtin_vpair_f64_fms): Likewise. + (__builtin_vpair_f64_nfma): Likewise. + * config/rs6000/rs6000/rs6000-proto.h (enum vpair_split_fma): New + enumeration. + (vpair_split_fma): New declaration. + * config/rs6000/rs6000.cc (vpair_split_fma): New function to split + vector pair FMA operations. + * config/rs6000/vector-pair.md (UNSPEC_VPAIR_FMA): New unspec. + (vpair_stdname): Add UNSPEC_VPAIR_FMA. + (VPAIR_OP): Likewise. + (vpair_fma_<vpair_modename>4): New insns. + (vpair_fms_<vpair_modename>4): Likewise. + (vpair_nfma_<vpair_modename>4): Likewise. + (vpair_nfms_<vpair_modename>4): Likewise. + * doc/extend.texi (PowerPC Vector Pair Built-in Functions): Document new + vector pair fma built-in functions. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-pair-3.c: New test. + * gcc.target/powerpc/vector-pair-4.c: Likewise. + +==================== Branch work154-acombo, work154-pair patch #201 ==================== + +Add support for vector pair unary and binary operations. + +2024-01-23 Michael Meissner <meissner@linux.ibm.com> + +gcc/ + + * config/rs6000/rs6000-builtins.def (__builtin_vpair_*): Add new + built-in functions for vector pair support. + * config/rs6000/rs6000-protos.h (enum vpair_split_unary): New + enumeration. + (vpair_split_unary): New declaration. + (vpair_split_binary): Likewise. + * config/rs6000/rs6000.cc (vpair_split_unary): New function to split + vector pair operations. + (vpair_split_binary): Likewise. + * config/rs6000/rs6000.md (toplevel): Include vector-pair.md. + * config/rs6000/t-rs6000 (MD_INCLUDES): Add vector-pair.md. + * config/rs6000/vector-pair.md: New file. + * doc/extend.texi (PowerPC Vector Pair Built-in Functions): Add + documentation for the new vector pair built-in functions. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-pair-1.c: New test. + * gcc.target/powerpc/vector-pair-2.c: Likewise. + +==================== Branch work154-acombo, work154-ajit patch #400 ==================== + +ajit patch to generate lxvp. + +Hello All: + +This pass is registered before ira rtl pass. +Bootstrapped and regtested for powerpc64-linux-gnu. + +No regressions for spec 2017 benchmarks and improvements for some of the +FP and INT benchmarks. + +Vladimir: + +I did modify IRA and LRA register Allocators. Please review. + +Thanks & Regards +Ajit + +rs6000: New pass for replacement of adjacent lxv with lxvp. + +New pass to replace adjacent memory addresses lxv with lxvp. +This pass is registered before ira rtl pass. + +2024-01-23 Ajit Kumar Agarwal <aagarwa1@linux.ibm.com> + +gcc/ChangeLog: + + * config/rs6000/rs6000-passes.def: Registered vecload pass. + * config/rs6000/rs6000-vecload-opt.cc: Add new pass. + * config.gcc: Add new executable. + * config/rs6000/rs6000-protos.h: Add new prototype for vecload + pass. + * config/rs6000/rs6000.cc: Add new prototype for vecload pass. + * config/rs6000/t-rs6000: Add new rule. + * ira-color.cc: Form register pair with adjacent loads. + * lra-assigns.cc: Skip modifying register pair assignment. + * lra-int.h: Add pseudo_conflict field in lra_reg_p structure. + * lra.cc: Initialize pseudo_conflict field. + * ira-build.cc: Use of REG_FREQ. + +gcc/testsuite/ChangeLog: + + * g++.target/powerpc/vecload.C: New test. + * g++.target/powerpc/vecload1.C: New test. + * gcc.target/powerpc/mma-builtin-1.c: Modify test. + +==================== Branch work154-acombo, work154 patch #2 ==================== + +PR target/112886, Add %S<n> to print_operand for vector pair support. + +In looking at support for load vector pair and store vector pair for the +PowerPC in GCC, I noticed that we were missing a print_operand output modifier +if you are dealing with vector pairs to print the 2nd register in the vector +pair. + +If the instruction inside of the asm used the Altivec encoding, then we could +use the %L<n> modifier: + + __vector_pair *p, *q, *r; + // ... + __asm__ ("vaddudm %0,%1,%2\n\tvaddudm %L0,%L1,%L2" + : "=v" (*p) + : "v" (*q), "v" (*r)); + +Likewise if we know the value to be in a tradiational FPR register, %L<n> will +work for instructions that use the VSX encoding: + + __vector_pair *p, *q, *r; + // ... + __asm__ ("xvadddp %x0,%x1,%x2\n\txvadddp %L0,%L1,%L2" + : "=f" (*p) + : "f" (*q), "f" (*r)); + +But if have a value that is in a traditional Altivec register, and the +instruction uses the VSX encoding, %L<n> will a value between 0 and 31, when it +should give a value between 32 and 63. + +This patch adds %S<n> that acts like %x<n>, except that it adds 1 to the +register number. + +I have tested this on power10 and power9 little endian systems and on a power9 +big endian system. There were no regressions in the patch. Can I apply it to +the trunk? + +It would be nice if I could apply it to the open branches. Can I backport it +after a burn-in period? + +2024-01-23 Michael Meissner <meissner@linux.ibm.com> + +gcc/ + + PR target/112886 + * config/rs6000/rs6000.cc (print_operand): Add %S<n> output modifier. + * doc/md.texi (Modifiers): Mention %S can be used like %x. + +gcc/testsuite/ + + PR target/112886 + * /gcc.target/powerpc/pr112886.c: New test. + +==================== Branch work154-acombo, work154 patch #1 ==================== + +Power10: Add options to disable load and store vector pair. + +This is version 2 of the patch to add -mno-load-vector-pair and +-mno-store-vector-pair undocumented tuning switches. + +The differences between the first version of the patch and this version is that +I added explicit RTL abi attributes for when the compiler can generate the load +vector pair and store vector pair instructions. By having this attribute, the +movoo insn has separate alternatives for when we generate the instruction and +when we want to split the instruction into 2 separate vector loads or stores. + +In the first version of the patch, I had previously provided built-in functions +that would always generate load vector pair and store vector pair instructions +even if these instructions are normally disabled. I found these built-ins +weren't specified like the other vector pair built-ins, and I didn't include +documentation for the built-in functions. If we want such built-in functions, +we can add them as a separate patch later. + +In addition, since both versions of the patch adds #pragma target and attribute +support to change the results for individual functions, we can select on a +function by function basis what the defaults for load/store vector pair is. + +The original text for the patch is: + +In working on some future patches that involve utilizing vector pair +instructions, I wanted to be able to tune my program to enable or disable using +the vector pair load or store operations while still keeping the other +operations on the vector pair. + +This patch adds two undocumented tuning options. The -mno-load-vector-pair +option would tell GCC to generate two load vector instructions instead of a +single load vector pair. The -mno-store-vector-pair option would tell GCC to +generate two store vector instructions instead of a single store vector pair. + +If either -mno-load-vector-pair is used, GCC will not generate the indexed +stxvpx instruction. Similarly if -mno-store-vector-pair is used, GCC will not +generate the indexed lxvpx instruction. The reason for this is to enable +splitting the {,p}lxvp or {,p}stxvp instructions after reload without needing a +scratch GPR register. + +The default for -mcpu=power10 is that both load vector pair and store vector +pair are enabled. + +I added code so that the user code can modify these settings using either a +'#pragma GCC target' directive or used __attribute__((__target__(...))) in the +function declaration. + +I added tests for the switches, #pragma, and attribute options. + +I have built this on both little endian power10 systems and big endian power9 +systems doing the normal bootstrap and test. There were no regressions in any +of the tests, and the new tests passed. Can I check this patch into the master +branch? + +2024-01-23 Michael Meissner <meissner@linux.ibm.com> + +gcc/ + + * config/rs6000/mma.md (movoo): Add support for -mno-load-vector-pair and + -mno-store-vector-pair. + * config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add support for + -mload-vector-pair and -mstore-vector-pair. + (POWERPC_MASKS): Likewise. + * config/rs6000/rs6000.cc (rs6000_setup_reg_addr_masks): Only allow + indexed mode for OOmode if we are generating both load vector pair and + store vector pair instructions. + (rs6000_option_override_internal): Add support for -mno-load-vector-pair + and -mno-store-vector-pair. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.md (isa attribute): Add lxvp and stxvp + attributes. + (enabled attribute): Likewise. + * config/rs6000/rs6000.opt (-mload-vector-pair): New option. + (-mstore-vector-pair): Likewise. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-pair-attribute.c: New test. + * gcc.target/powerpc/vector-pair-pragma.c: New test. + * gcc.target/powerpc/vector-pair-switch1.c: New test. + * gcc.target/powerpc/vector-pair-switch2.c: New test. + * gcc.target/powerpc/vector-pair-switch3.c: New test. + * gcc.target/powerpc/vector-pair-switch4.c: New test. + ==================== Branch work154-acombo, baseline ==================== +Add ChangeLog.acombo and update REVISION. + +2024-01-22 Michael Meissner <meissner@linux.ibm.com> + +gcc/ + + * ChangeLog.acombo: New file for branch. + * REVISION: Update. + 2024-01-22 Michael Meissner <meissner@linux.ibm.com> Clone branch -
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