From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2119) id EB9A6385803D; Wed, 24 Jan 2024 17:20:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EB9A6385803D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1706116813; bh=4t8fbcdf6qnch9IDIYRm9hqLWGdZN4zYSlajl3UKs6s=; h=From:To:Subject:Date:From; b=e5BFLAsKBzO+SlEIXGr1mYOAoDUCMuIESaswNYId29iVW5AGyJGXIVnilatpOqmho UnO6VPEF2TdgAC1dLgU/dxWtMJfBEkdSGAgw4o2DwQMgIFibpRV5+I1q16UC0bcOSU kQV1STYfJxBeDP5wb/IYIIFqt6gMH96Q1/msNM7s= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Jeff Law To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-8396] [PATCH v3] RISC-V: Add split pattern to generate SFB instructions. [PR113095] X-Act-Checkin: gcc X-Git-Author: Monk Chiang X-Git-Refname: refs/heads/master X-Git-Oldrev: 0f5a9a00e3ab1fe96142f304cfbcf3f63b15f326 X-Git-Newrev: fb54b9772816968032518d4008be5090e0d95109 Message-Id: <20240124172013.EB9A6385803D@sourceware.org> Date: Wed, 24 Jan 2024 17:20:13 +0000 (GMT) List-Id: https://gcc.gnu.org/g:fb54b9772816968032518d4008be5090e0d95109 commit r14-8396-gfb54b9772816968032518d4008be5090e0d95109 Author: Monk Chiang Date: Wed Jan 24 10:19:28 2024 -0700 [PATCH v3] RISC-V: Add split pattern to generate SFB instructions. [PR113095] Since the match.pd transforms (zero_one == 0) ? y : z y, into ((typeof(y))zero_one * z) y. Add splitters to recongize this expression to generate SFB instructions. gcc/ChangeLog: PR target/113095 * config/riscv/sfb.md: New splitters to rewrite single bit sign extension as the condition to SFB instructions. gcc/testsuite/ChangeLog: * gcc.target/riscv/sfb.c: New test. * gcc.target/riscv/pr113095.c: New test. Diff: --- gcc/config/riscv/sfb.md | 32 +++++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/pr113095.c | 21 ++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/sfb.c | 24 +++++++++++++++++++++++ 3 files changed, 77 insertions(+) diff --git a/gcc/config/riscv/sfb.md b/gcc/config/riscv/sfb.md index 8ab747142c8..bfd229e3d09 100644 --- a/gcc/config/riscv/sfb.md +++ b/gcc/config/riscv/sfb.md @@ -35,3 +35,35 @@ [(set_attr "length" "8") (set_attr "type" "sfb_alu") (set_attr "mode" "")]) + +;; Combine creates this form ((typeof(y))zero_one * z) y +;; for SiFive short forward branches. + +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_SFB_ALU" + [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (if_then_else:X (ne (match_dup 4) (const_int 0)) + (match_dup 3) + (const_int 0)))]) + +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)" + [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2))) + (set (match_dup 0) (if_then_else:X (ne (match_dup 4) (const_int 0)) + (match_dup 3) + (const_int 0)))] +{ + operands[2] = GEN_INT (1 << UINTVAL(operands[2])); +}) diff --git a/gcc/testsuite/gcc.target/riscv/pr113095.c b/gcc/testsuite/gcc.target/riscv/pr113095.c new file mode 100644 index 00000000000..04321b58dc7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr113095.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -march=rv32gc -mabi=ilp32d -mtune=sifive-7-series" { target { rv32 } } } */ +/* { dg-options "-O2 -march=rv64gc -mabi=lp64d -mtune=sifive-7-series" {target { rv64 } } } */ + +extern void abort (void); +extern void exit (int); + +unsigned short __attribute__ ((noinline, noclone)) +foo (unsigned short x) { + if (x == 1) + x ^= 0x4002; + + return x; +} + +int main () { + if (foo(1) != 0x4003) + abort (); + + exit(0); +} diff --git a/gcc/testsuite/gcc.target/riscv/sfb.c b/gcc/testsuite/gcc.target/riscv/sfb.c new file mode 100644 index 00000000000..22f164051f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sfb.c @@ -0,0 +1,24 @@ +//* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc -mabi=ilp32d -mtune=sifive-7-series" } */ + +int f1(unsigned int x, unsigned int y, unsigned int z) +{ + return ((x & 1) == 0) ? y : z ^ y; +} + +int f2(unsigned int x, unsigned int y, unsigned int z) +{ + return ((x & 1) != 0) ? z ^ y : y; +} + +int f3(unsigned int x, unsigned int y, unsigned int z) +{ + return ((x & 1) == 0) ? y : z | y; +} + +int f4(unsigned int x, unsigned int y, unsigned int z) +{ + return ((x & 1) != 0) ? z | y : y; +} +/* { dg-final { scan-assembler-times "bne" 4 } } */ +/* { dg-final { scan-assembler-times "movcc" 4 } } */