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From: Richard Earnshaw <rearnsha@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r14-8499] arm: Add pattern for bswap + rotate -> rev16 [Bug 108933] Date: Mon, 29 Jan 2024 15:58:31 +0000 (GMT) [thread overview] Message-ID: <20240129155831.2A7853858430@sourceware.org> (raw) https://gcc.gnu.org/g:bad991a1c5960e90c4686a9362a1258ef29e195b commit r14-8499-gbad991a1c5960e90c4686a9362a1258ef29e195b Author: Matthieu Longo <matthieu.longo@arm.com> Date: Mon Jan 29 15:54:35 2024 +0000 arm: Add pattern for bswap + rotate -> rev16 [Bug 108933] The rev16 pattern was not recognised anymore as a change in the bswap tree pass was introducing a new GIMPLE form, not recognized by the assembly final transformation pass. Also, fix the output patterns for arm_rev16si_alt[12] to correctly handle the instructions being made conditional. More details in the PR. gcc/ChangeLog: PR target/108933 * config/arm/arm.md (arm_rev16si2): Convert to define_insn. Correct generated RTL. (arm_rev16si2_alt1): Correctly handle conditional execution. (arm_rev16si2_alt2): Likewise. gcc/testsuite/ChangeLog: PR target/108933 * gcc.target/arm/rev16.c: Moved to... * gcc.target/arm/rev16_1.c: ...here. * gcc.target/arm/rev16_2.c: New test to check that rev16 is emitted. Diff: --- gcc/config/arm/arm.md | 31 ++++++++++++++-------- .../gcc.target/arm/{rev16.c => rev16_1.c} | 0 gcc/testsuite/gcc.target/arm/rev16_2.c | 20 ++++++++++++++ 3 files changed, 40 insertions(+), 11 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 4a98f2d7b625..5816409f86f1 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12578,7 +12578,10 @@ "arm_arch6 && aarch_rev16_shleft_mask_imm_p (operands[3], SImode) && aarch_rev16_shright_mask_imm_p (operands[2], SImode)" - "rev16\\t%0, %1" + "@ + rev16\t%0, %1 + rev16%?\t%0, %1 + rev16%?\t%0, %1" [(set_attr "arch" "t1,t2,32") (set_attr "length" "2,2,4") (set_attr "type" "rev")] @@ -12595,22 +12598,28 @@ "arm_arch6 && aarch_rev16_shleft_mask_imm_p (operands[3], SImode) && aarch_rev16_shright_mask_imm_p (operands[2], SImode)" - "rev16\\t%0, %1" + "@ + rev16\t%0, %1 + rev16%?\t%0, %1 + rev16%?\t%0, %1" [(set_attr "arch" "t1,t2,32") (set_attr "length" "2,2,4") (set_attr "type" "rev")] ) -(define_expand "arm_rev16si2" - [(set (match_operand:SI 0 "s_register_operand") - (bswap:SI (match_operand:SI 1 "s_register_operand")))] +;; Similar pattern to match (rotate (bswap) 16) +(define_insn "arm_rev16si2" + [(set (match_operand:SI 0 "register_operand" "=l,l,r") + (rotate:SI (bswap:SI (match_operand:SI 1 "register_operand" "l,l,r")) + (const_int 16)))] "arm_arch6" - { - rtx left = gen_int_mode (HOST_WIDE_INT_C (0xff00ff00ff00ff00), SImode); - rtx right = gen_int_mode (HOST_WIDE_INT_C (0xff00ff00ff00ff), SImode); - emit_insn (gen_arm_rev16si2_alt1 (operands[0], operands[1], right, left)); - DONE; - } + "@ + rev16\t%0, %1 + rev16%?\t%0, %1 + rev16%?\t%0, %1" + [(set_attr "arch" "t1,t2,32") + (set_attr "length" "2,2,4") + (set_attr "type" "rev")] ) (define_expand "bswaphi2" diff --git a/gcc/testsuite/gcc.target/arm/rev16.c b/gcc/testsuite/gcc.target/arm/rev16_1.c similarity index 100% rename from gcc/testsuite/gcc.target/arm/rev16.c rename to gcc/testsuite/gcc.target/arm/rev16_1.c diff --git a/gcc/testsuite/gcc.target/arm/rev16_2.c b/gcc/testsuite/gcc.target/arm/rev16_2.c new file mode 100644 index 000000000000..c6553b38a000 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/rev16_2.c @@ -0,0 +1,20 @@ +/* { dg-options "-O2" } */ +/* { dg-do compile } */ + +typedef unsigned int __u32; + +__u32 +__rev16_32_alt (__u32 x) +{ + return (((__u32)(x) & (__u32)0xff00ff00UL) >> 8) + | (((__u32)(x) & (__u32)0x00ff00ffUL) << 8); +} + +__u32 +__rev16_32 (__u32 x) +{ + return (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) + | (((__u32)(x) & (__u32)0xff00ff00UL) >> 8); +} + +/* { dg-final { scan-assembler-times {rev16\tr[0-9]+, r[0-9]+} 2 } } */
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