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* [gcc(refs/users/meissner/heads/work154-test)] Update ChangeLog.*
@ 2024-01-31 2:17 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2024-01-31 2:17 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7b44dc013bbd3f0dc50f103780d020e47b03ea39
commit 7b44dc013bbd3f0dc50f103780d020e47b03ea39
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Jan 30 21:17:54 2024 -0500
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.test | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index 993205193188..a04c741eb1c7 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,3 +1,16 @@
+==================== Branch work154-test, patch #705 ====================
+
+Fix power11 tests #3.
+
+2024-01-30 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/power11-1.c: Rewite;
+ * gcc.target/powerpc/power11-2.c: Rewite;
+ * gcc.target/powerpc/power11-3.c: Rewite;
+ * lib/target-supports.exp (check_effective_target_power11_ok): Rewrite.
+
==================== Branch work154-test, patch #704 ====================
Fix power11 tests #2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work154-test)] Update ChangeLog.*
@ 2024-01-31 19:33 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2024-01-31 19:33 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:78e4276e2c23cf4f86c893bcb2041d4d13ea3463
commit 78e4276e2c23cf4f86c893bcb2041d4d13ea3463
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Jan 31 14:32:59 2024 -0500
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.test | 84 +++++++++++++++++-------------------------------------
1 file changed, 26 insertions(+), 58 deletions(-)
diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index c1eacec7b2e0..b920123f8bd6 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,67 +1,26 @@
-==================== Branch work154-test, patch #706 ====================
+==================== Branch work154-test, patch #710 ====================
-Fix power11 tests #4.
-
-2024-01-30 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/testsuite/
-
- * gcc.target/powerpc/power11-1.c: Use correct target.
- * gcc.target/powerpc/power11-2.c: Likewise.
- * gcc.target/powerpc/power11-3.c: Likewise.
-
-==================== Branch work154-test, patch #705 ====================
-
-Fix power11 tests #3.
-
-2024-01-30 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/testsuite/
-
- * gcc.target/powerpc/power11-1.c: Rewite;
- * gcc.target/powerpc/power11-2.c: Rewite;
- * gcc.target/powerpc/power11-3.c: Rewite;
- * lib/target-supports.exp (check_effective_target_power11_ok): Rewrite.
-
-==================== Branch work154-test, patch #704 ====================
-
-Fix power11 tests #2
-
-2024-01-30 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/testsuite/
-
- * lib/target-supports.exp (check_effective_target_power11_ok): Fix typo.
-
-==================== Branch work154-test, patch #703 ====================
-
-Fix power11 tests #1.
-
-2024-01-30 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/testsuite/
+Initial power11 patch.
- * lib/target-supports.exp (check_effective_target_power11_ok): Fix typo.
+This patch adds -mcpu=power11 support.
-==================== Branch work154-test, patch #702 ====================
+I did not add a separate PROCESSOR_POWER11 since power11 will generate exactly
+the same code as power10. I did put a comment into rs6000-opts.h why we did
+not create PROCESSOR_POWER11.
-Add power11 tests.
+I used an option bit in rs6000_isa_flags to signal that we should put out a
+".machine power11" instead of ".machine power10" and also define _ARCH_PWR11.
-2024-01-30 Michael Meissner <meissner@linux.ibm.com>
+We could have a separate variable to hold the power11 status, but this would
+require adding a lot of code that would be needed when we change the cpu via
+attribute/pragma target and attribute target_clones. We would need to pass
+additional arguments to the function rs6000_machine_from_flags and
+rs6000_target_modify_macros which only take the isa flags variable.
-gcc/testsuite/
+I added some test cases to verify that -mcpu=power11, and that we can set
+power11 via a target attribute/pragma or via target_clones attribute.
- * gcc.target/powerpc/power11-1.c: New test.
- * gcc.target/powerpc/power11-2.c: Likewise.
- * gcc.target/powerpc/power11-3.c: Likewise.
- * lib/target-supports.exp (check_effective_target_power11_ok): Add
- power11 support.
-
-==================== Branch work154-test, patch #701 ====================
-
-Initial power11 patch.
-
-2024-01-25 Michael Meissner <meissner@linux.ibm.com>
+2024-01-31 Michael Meissner <meissner@linux.ibm.com>
gcc/
@@ -88,7 +47,16 @@ gcc/
* config/rs6000/rs6000.opt (-mpower11): Dummy option to flag
-mcpu=power11.
* doc/invoke.texi (PowerPC options): Document -mcpu=power11.
- * doc/invoke.texi: Ditto.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/power11-1.c: New test.
+ * gcc.target/powerpc/power11-2.c: Likewise.
+ * gcc.target/powerpc/power11-3.c: Likewise.
+ * lib/target-supports.exp (check_effective_target_power11_ok): Add
+ power11 support.
+
+==================== Branch work154-test, patches #706-700 were reverted ====================
==================== Branch work154-test, patch #2 from work154 ====================
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work154-test)] Update ChangeLog.*
@ 2024-01-31 3:53 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2024-01-31 3:53 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3e3706f393139f4d99edd868d6d7592f6b15e92d
commit 3e3706f393139f4d99edd868d6d7592f6b15e92d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Jan 30 22:53:52 2024 -0500
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.test | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index a04c741eb1c7..c1eacec7b2e0 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,3 +1,15 @@
+==================== Branch work154-test, patch #706 ====================
+
+Fix power11 tests #4.
+
+2024-01-30 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/power11-1.c: Use correct target.
+ * gcc.target/powerpc/power11-2.c: Likewise.
+ * gcc.target/powerpc/power11-3.c: Likewise.
+
==================== Branch work154-test, patch #705 ====================
Fix power11 tests #3.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work154-test)] Update ChangeLog.*
@ 2024-01-31 0:27 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2024-01-31 0:27 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5a566f693fab13d418a0bd0fbf7ee45bc8229505
commit 5a566f693fab13d418a0bd0fbf7ee45bc8229505
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Jan 30 19:27:48 2024 -0500
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.test | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index a1258ac74460..993205193188 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,6 +1,16 @@
+==================== Branch work154-test, patch #704 ====================
+
+Fix power11 tests #2
+
+2024-01-30 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+ * lib/target-supports.exp (check_effective_target_power11_ok): Fix typo.
+
==================== Branch work154-test, patch #703 ====================
-Add power11 tests.
+Fix power11 tests #1.
2024-01-30 Michael Meissner <meissner@linux.ibm.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work154-test)] Update ChangeLog.*
@ 2024-01-31 0:22 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2024-01-31 0:22 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:e9239f22dd10f2a2a63a96745924e5ed5dbe03d0
commit e9239f22dd10f2a2a63a96745924e5ed5dbe03d0
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Jan 30 19:22:03 2024 -0500
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.test | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index 4db02e01206b..a1258ac74460 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,3 +1,13 @@
+==================== Branch work154-test, patch #703 ====================
+
+Add power11 tests.
+
+2024-01-30 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+ * lib/target-supports.exp (check_effective_target_power11_ok): Fix typo.
+
==================== Branch work154-test, patch #702 ====================
Add power11 tests.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work154-test)] Update ChangeLog.*
@ 2024-01-30 22:19 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2024-01-30 22:19 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7902e9af6de9124dfcfe9b9c9fe5f3653e0bc55d
commit 7902e9af6de9124dfcfe9b9c9fe5f3653e0bc55d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Jan 30 17:19:21 2024 -0500
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.test | 199 +++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 199 insertions(+)
diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test
index 287bba9ee77c..4db02e01206b 100644
--- a/gcc/ChangeLog.test
+++ b/gcc/ChangeLog.test
@@ -1,5 +1,204 @@
+==================== Branch work154-test, patch #702 ====================
+
+Add power11 tests.
+
+2024-01-30 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/power11-1.c: New test.
+ * gcc.target/powerpc/power11-2.c: Likewise.
+ * gcc.target/powerpc/power11-3.c: Likewise.
+ * lib/target-supports.exp (check_effective_target_power11_ok): Add
+ power11 support.
+
+==================== Branch work154-test, patch #701 ====================
+
+Initial power11 patch.
+
+2024-01-25 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config.gcc (powerpc*): Add power11 support.
+ * config/rs6000/driver-rs6000.cc (asm_names): Pass -mpwr11 to assember
+ if power11.
+ * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER10): Remove comment saying
+ power10 platform number is unofficial.
+ (PPC_PLATFORM_POWER11): Add new value for power11.
+ * config/rs6000/rs6000-builtin.cc (cpu_is_info): Add support for
+ generating .machine power11.
+ * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+ _ARCH_PWR11 if -mcpu=power11.
+ * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add
+ OPTION_MASK_POWER11.
+ (power11 cpu): Define.
+ * config/rs6000/rs6000-opts.h (enum processor_type): Add comment about
+ not adding PROCESSOR_POWER11.
+ * config/rs6000/rs6000-tables.opt: Regenerate.
+ * config/rs6000/rs6000.cc (rs6000_machine_from_flags): Add power11
+ support.
+ (rs6000_opt_masks): Likewise.
+ * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add -mcpu=power11 support.
+ * config/rs6000/rs6000.opt (-mpower11): Dummy option to flag
+ -mcpu=power11.
+ * doc/invoke.texi (PowerPC options): Document -mcpu=power11.
+ * doc/invoke.texi: Ditto.
+
+==================== Branch work154-test, patch #2 from work154 ====================
+
+PR target/112886, Add %S<n> to print_operand for vector pair support.
+
+In looking at support for load vector pair and store vector pair for the
+PowerPC in GCC, I noticed that we were missing a print_operand output modifier
+if you are dealing with vector pairs to print the 2nd register in the vector
+pair.
+
+If the instruction inside of the asm used the Altivec encoding, then we could
+use the %L<n> modifier:
+
+ __vector_pair *p, *q, *r;
+ // ...
+ __asm__ ("vaddudm %0,%1,%2\n\tvaddudm %L0,%L1,%L2"
+ : "=v" (*p)
+ : "v" (*q), "v" (*r));
+
+Likewise if we know the value to be in a tradiational FPR register, %L<n> will
+work for instructions that use the VSX encoding:
+
+ __vector_pair *p, *q, *r;
+ // ...
+ __asm__ ("xvadddp %x0,%x1,%x2\n\txvadddp %L0,%L1,%L2"
+ : "=f" (*p)
+ : "f" (*q), "f" (*r));
+
+But if have a value that is in a traditional Altivec register, and the
+instruction uses the VSX encoding, %L<n> will a value between 0 and 31, when it
+should give a value between 32 and 63.
+
+This patch adds %S<n> that acts like %x<n>, except that it adds 1 to the
+register number.
+
+This is version 2 of the patch. The only difference is I made the test case
+simpler to read.
+
+I have tested this on power10 and power9 little endian systems and on a power9
+big endian system. There were no regressions in the patch. Can I apply it to
+the trunk?
+
+It would be nice if I could apply it to the open branches. Can I backport it
+after a burn-in period?
+
+2024-01-22 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ PR target/112886
+ * config/rs6000/rs6000.cc (print_operand): Add %S<n> output modifier.
+ * doc/md.texi (Modifiers): Mention %S can be used like %x.
+
+gcc/testsuite/
+
+ PR target/112886
+ * /gcc.target/powerpc/pr112886.c: New test.
+
+==================== Branch work154-test, patch #1 from work154 ====================
+
+Power10: Add options to disable load and store vector pair.
+
+This is version 2 of the patch to add -mno-load-vector-pair and
+-mno-store-vector-pair undocumented tuning switches.
+
+The differences between the first version of the patch and this version is that
+I added explicit RTL abi attributes for when the compiler can generate the load
+vector pair and store vector pair instructions. By having this attribute, the
+movoo insn has separate alternatives for when we generate the instruction and
+when we want to split the instruction into 2 separate vector loads or stores.
+
+In the first version of the patch, I had previously provided built-in functions
+that would always generate load vector pair and store vector pair instructions
+even if these instructions are normally disabled. I found these built-ins
+weren't specified like the other vector pair built-ins, and I didn't include
+documentation for the built-in functions. If we want such built-in functions,
+we can add them as a separate patch later.
+
+In addition, since both versions of the patch adds #pragma target and attribute
+support to change the results for individual functions, we can select on a
+function by function basis what the defaults for load/store vector pair is.
+
+The original text for the patch is:
+
+In working on some future patches that involve utilizing vector pair
+instructions, I wanted to be able to tune my program to enable or disable using
+the vector pair load or store operations while still keeping the other
+operations on the vector pair.
+
+This patch adds two undocumented tuning options. The -mno-load-vector-pair
+option would tell GCC to generate two load vector instructions instead of a
+single load vector pair. The -mno-store-vector-pair option would tell GCC to
+generate two store vector instructions instead of a single store vector pair.
+
+If either -mno-load-vector-pair is used, GCC will not generate the indexed
+stxvpx instruction. Similarly if -mno-store-vector-pair is used, GCC will not
+generate the indexed lxvpx instruction. The reason for this is to enable
+splitting the {,p}lxvp or {,p}stxvp instructions after reload without needing a
+scratch GPR register.
+
+The default for -mcpu=power10 is that both load vector pair and store vector
+pair are enabled.
+
+I added code so that the user code can modify these settings using either a
+'#pragma GCC target' directive or used __attribute__((__target__(...))) in the
+function declaration.
+
+I added tests for the switches, #pragma, and attribute options.
+
+I have built this on both little endian power10 systems and big endian power9
+systems doing the normal bootstrap and test. There were no regressions in any
+of the tests, and the new tests passed. Can I check this patch into the master
+branch?
+
+2024-01-23 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/mma.md (movoo): Add support for -mno-load-vector-pair and
+ -mno-store-vector-pair.
+ * config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add support for
+ -mload-vector-pair and -mstore-vector-pair.
+ (POWERPC_MASKS): Likewise.
+ * config/rs6000/rs6000.cc (rs6000_setup_reg_addr_masks): Only allow
+ indexed mode for OOmode if we are generating both load vector pair and
+ store vector pair instructions.
+ (rs6000_option_override_internal): Add support for -mno-load-vector-pair
+ and -mno-store-vector-pair.
+ (rs6000_opt_masks): Likewise.
+ * config/rs6000/rs6000.md (isa attribute): Add lxvp and stxvp
+ attributes.
+ (enabled attribute): Likewise.
+ * config/rs6000/rs6000.opt (-mload-vector-pair): New option.
+ (-mstore-vector-pair): Likewise.
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/vector-pair-attribute.c: New test.
+ * gcc.target/powerpc/vector-pair-pragma.c: New test.
+ * gcc.target/powerpc/vector-pair-switch1.c: New test.
+ * gcc.target/powerpc/vector-pair-switch2.c: New test.
+ * gcc.target/powerpc/vector-pair-switch3.c: New test.
+ * gcc.target/powerpc/vector-pair-switch4.c: New test.
+
==================== Branch work154-test, baseline ====================
+Add ChangeLog.test and update REVISION.
+
+2024-01-22 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * ChangeLog.test: New file for branch.
+ * REVISION: Update.
+
2024-01-22 Michael Meissner <meissner@linux.ibm.com>
Clone branch
^ permalink raw reply [flat|nested] 6+ messages in thread
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