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* [gcc r14-8677] Revert "RISC-V: Use default cost model for insn scheduling"
@ 2024-02-01 5:53 Edwin Lu
0 siblings, 0 replies; only message in thread
From: Edwin Lu @ 2024-02-01 5:53 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:017b4c2a4977a8e50a336e4fef8c4ef817765033
commit r14-8677-g017b4c2a4977a8e50a336e4fef8c4ef817765033
Author: Edwin Lu <ewlu@rivosinc.com>
Date: Wed Jan 31 21:49:25 2024 -0800
Revert "RISC-V: Use default cost model for insn scheduling"
This reverts commit 4b799a16ae59fc0f508c5931ebf1851a3446b707.
Diff:
---
gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C | 2 --
gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 2 --
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 2 --
gcc/testsuite/gfortran.dg/vect/vect-8.f90 | 2 --
58 files changed, 116 deletions(-)
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C
index 6f62a64224dc..c1070f9eb16a 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
template < class T >
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
index 17a6b6f27fd1..7be22d60bf26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "reduc_call-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
index 8386b42e9b56..4b24b971cbac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
index e2ed4b76a16b..99acc51b4ffb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
index 61340be8362d..d595c4465030 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
index 0f1485e3c0a5..0b51175f66ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, uint64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
index 173ac625ada5..634c12a4c0e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
index 1edba8980b46..651d61001c14 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
index 75340c3da6c9..d19a9fda2356 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
index 7e4aedc1cdc8..16f431542d8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
index 755e92a9cd71..347c846dcbbc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
index 2c82dc0688a9..bc414440ba29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
index e2ac6a3d9e1b..ce3f3af9c3d1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
index 436a0e85f3d3..4946f84b9162 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
index 72b321607c33..5f2eede04221 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
index 72b321607c33..5f2eede04221 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
index 6908c78e19b2..88fcba60345e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
index 6908c78e19b2..88fcba60345e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
index ee1db1c41aed..87a16453feab 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
index fb969eb50a27..c0321cefb9a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
index 542f43eca49f..ab0f13ba255e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
index 31109a81ec35..3893e17511db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
index 924f4507ba35..b0ea553bf892 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
index 659d8d9e7020..350697d764dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
index 63874605759b..0f138c5d3c6e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
index a214d70cb2c7..f4cbf0953576 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
index efa659b2752b..d606078e85f6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
index 6a26248096dd..9bf9ff59de7a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
index 429fe1290038..bca55b239f97 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, uint64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
index 0cd0af761869..586e26499db2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
index bb1690e81e41..d1bbb78f5edc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
index 37ef0f054233..7e7387839740 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
index 4c6e88e7eed8..c3d0b10271a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
index 0844e3e87131..bd13ba916dae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
index 49a574485fed..99928f7b1ccd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
index cef0a11b2d44..321cd5c818ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gc_zve64d -mabi=lp64 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
index 3f0d67726bc8..575a7842cdf2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
index 4ed658899f4c..95a11d370168 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
index 95b7ff976666..8f6f0b11f09d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
index 9e0b41ccba70..250e017cc862 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
index 5e1859cd13b0..110e55b3cbeb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
index f4f0e52971ab..4583504bd5a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
index 7e01b81682b5..f16f4b9c37d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
index 5615cb1f97f0..43b443be6cbf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
index c906b153ab85..67855581fb2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
index 006df7edf8d6..960c9bff7651 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
index cc6d8221516b..5f22e8d0e8eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
index 9704e444d543..e5f35c0f018c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
index 476735dcb2e4..0532c7d42072 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
index c7b7db338496..b664c4b67eb1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
index 80ff75f6d2af..04c4b886eecd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
index 127dc7ff06de..1404c9dc0d54 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
index 127dc7ff06de..1404c9dc0d54 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
index e19e869e2413..609c68dfcbee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
index 90eca5b1ae68..043f17737ae3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
index 17b217bc82ce..0bedde84005f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
index 17b217bc82ce..0bedde84005f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
-// PR113249
-/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gfortran.dg/vect/vect-8.f90 b/gcc/testsuite/gfortran.dg/vect/vect-8.f90
index f77ec9fb87a7..938dfc29754c 100644
--- a/gcc/testsuite/gfortran.dg/vect/vect-8.f90
+++ b/gcc/testsuite/gfortran.dg/vect/vect-8.f90
@@ -1,8 +1,6 @@
! { dg-do compile }
! { dg-require-effective-target vect_double }
! { dg-additional-options "-fno-tree-loop-distribute-patterns -finline-matmul-limit=0" }
-! PR113249
-! { dg-options "-fno-schedule-insns -fno-schedule-insns2" { target { riscv*-*-* } } }
module lfk_prec
integer, parameter :: dp=kind(1.d0)
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2024-02-01 5:53 [gcc r14-8677] Revert "RISC-V: Use default cost model for insn scheduling" Edwin Lu
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