[gcc r14-8706] hppa: Fix bug in atomic_storedi_1 pattern

[gcc r14-8706] hppa: Fix bug in atomic_storedi_1 pattern

[John David Anglin]

https://gcc.gnu.org/g:f26094751ebd8f8603a0e62a8f1aab6a99c932e9

commit r14-8706-gf26094751ebd8f8603a0e62a8f1aab6a99c932e9
Author: John David Anglin <danglin@gcc.gnu.org>
Date:   Thu Feb 1 18:46:47 2024 +0000

    hppa: Fix bug in atomic_storedi_1 pattern
    
    The first alternative stores the floating-point status register
    in the destination.  It should store zero.  We need to copy %fr0
    to another floating-point register to initialize it to zero.
    
    2024-02-01  John David Anglin  <danglin@gcc.gnu.org>
    
    gcc/ChangeLog:
    
            * config/pa/pa.md (atomic_storedi_1): Fix bug in
            alternative 1.

Diff:
---
 gcc/config/pa/pa.md | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 52ad0c3776d6..aecdcc98b6a8 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -10723,13 +10723,13 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
 (define_insn "atomic_storedi_1"
   [(set (mem:DI (match_operand:SI 0 "register_operand" "r,r"))
         (match_operand:DI 1 "reg_or_0_operand" "M,r"))
-   (clobber (match_scratch:DI 2 "=X,f"))]
+   (clobber (match_scratch:DI 2 "=f,f"))]
   "!TARGET_64BIT && !TARGET_SOFT_FLOAT"
   "@
-   {fstds|fstd} %%fr0,0(%0)
+   fcpy,dbl %%fr0,%2\n\t{fstds|fstd} %2,0(%0)
    {stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)"
   [(set_attr "type" "move,move")
-   (set_attr "length" "4,16")])
+   (set_attr "length" "8,16")])
 
 ;; PA 2.0 hardware supports out-of-order execution of loads and stores, so
 ;; we need memory barriers to enforce program order for memory references