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* [gcc r12-10133] MIPS: Fix wrong MSA FP vector negation
@ 2024-02-05 11:43 Xi Ruoyao
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From: Xi Ruoyao @ 2024-02-05 11:43 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:2d7ce7890e1687524c2a8a949e8d9c45d9182f10
commit r12-10133-g2d7ce7890e1687524c2a8a949e8d9c45d9182f10
Author: Xi Ruoyao <xry111@xry111.site>
Date: Sat Feb 3 03:35:07 2024 +0800
MIPS: Fix wrong MSA FP vector negation
We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is
wrong because -0.0 is not 0 - 0.0. This causes some Python tests to
fail when Python is built with MSA enabled.
Use the bnegi.df instructions to simply reverse the sign bit instead.
gcc/ChangeLog:
* config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
(neg<mode>2): Change the mode iterator from MSA to IMSA because
in FP arithmetic we cannot use (0 - x) for -x.
(neg<mode>2): New define_insn to implement FP vector negation,
using a bnegi instruction to negate the sign bit.
(cherry picked from commit 4d7fe3cf82505b45719356a2e51b1480b5ee21d6)
Diff:
---
gcc/config/mips/mips-msa.md | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
index cd4b6973847d..e142e0e1ed7e 100644
--- a/gcc/config/mips/mips-msa.md
+++ b/gcc/config/mips/mips-msa.md
@@ -231,6 +231,10 @@
(V4SI "uimm5")
(V2DI "uimm6")])
+;; The index of sign bit in FP vector elements.
+(define_mode_attr elmsgnbit [(V2DF "63") (V4DF "63")
+ (V4SF "31") (V8SF "31")])
+
(define_expand "vec_init<mode><unitmode>"
[(match_operand:MSA 0 "register_operand")
(match_operand:MSA 1 "")]
@@ -597,9 +601,9 @@
})
(define_expand "neg<mode>2"
- [(set (match_operand:MSA 0 "register_operand")
- (minus:MSA (match_dup 2)
- (match_operand:MSA 1 "register_operand")))]
+ [(set (match_operand:IMSA 0 "register_operand")
+ (minus:IMSA (match_dup 2)
+ (match_operand:IMSA 1 "register_operand")))]
"ISA_HAS_MSA"
{
rtx reg = gen_reg_rtx (<MODE>mode);
@@ -607,6 +611,14 @@
operands[2] = reg;
})
+(define_insn "neg<mode>2"
+ [(set (match_operand:FMSA 0 "register_operand" "=f")
+ (neg (match_operand:FMSA 1 "register_operand" "f")))]
+ "ISA_HAS_MSA"
+ "bnegi.<msafmt>\t%w0,%w1,<elmsgnbit>"
+ [(set_attr "type" "simd_bit")
+ (set_attr "mode" "<MODE>")])
+
(define_expand "msa_ldi<mode>"
[(match_operand:IMSA 0 "register_operand")
(match_operand 1 "const_imm10_operand")]
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