From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7856) id 8990C3858CDB; Mon, 5 Feb 2024 11:43:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8990C3858CDB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1707133412; bh=ypFXPoEDAC7P9QcewINGxq3yBvj2tvxqdimE7YKHRh8=; h=From:To:Subject:Date:From; b=bIUbhPqnDevzLy7JkHm9MrThCzBfZLdj1psbXvwjoqCwEeIpsekwkHgot+NQ41Px8 q/bL+8j3q0BUFJuVFachCxLwrZTLOS2OIIIrJQUOo3BYOOtNgQDyv2ugHq75PulZdf uehNuQ7gADFz0g2N1Z/to9qP4IYotbvflWZsy01c= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Xi Ruoyao To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-10133] MIPS: Fix wrong MSA FP vector negation X-Act-Checkin: gcc X-Git-Author: Xi Ruoyao X-Git-Refname: refs/heads/releases/gcc-12 X-Git-Oldrev: 0528af22a593c4a07872cddf83ddd44d70843789 X-Git-Newrev: 2d7ce7890e1687524c2a8a949e8d9c45d9182f10 Message-Id: <20240205114332.8990C3858CDB@sourceware.org> Date: Mon, 5 Feb 2024 11:43:32 +0000 (GMT) List-Id: https://gcc.gnu.org/g:2d7ce7890e1687524c2a8a949e8d9c45d9182f10 commit r12-10133-g2d7ce7890e1687524c2a8a949e8d9c45d9182f10 Author: Xi Ruoyao Date: Sat Feb 3 03:35:07 2024 +0800 MIPS: Fix wrong MSA FP vector negation We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is wrong because -0.0 is not 0 - 0.0. This causes some Python tests to fail when Python is built with MSA enabled. Use the bnegi.df instructions to simply reverse the sign bit instead. gcc/ChangeLog: * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr. (neg2): Change the mode iterator from MSA to IMSA because in FP arithmetic we cannot use (0 - x) for -x. (neg2): New define_insn to implement FP vector negation, using a bnegi instruction to negate the sign bit. (cherry picked from commit 4d7fe3cf82505b45719356a2e51b1480b5ee21d6) Diff: --- gcc/config/mips/mips-msa.md | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index cd4b6973847d..e142e0e1ed7e 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -231,6 +231,10 @@ (V4SI "uimm5") (V2DI "uimm6")]) +;; The index of sign bit in FP vector elements. +(define_mode_attr elmsgnbit [(V2DF "63") (V4DF "63") + (V4SF "31") (V8SF "31")]) + (define_expand "vec_init" [(match_operand:MSA 0 "register_operand") (match_operand:MSA 1 "")] @@ -597,9 +601,9 @@ }) (define_expand "neg2" - [(set (match_operand:MSA 0 "register_operand") - (minus:MSA (match_dup 2) - (match_operand:MSA 1 "register_operand")))] + [(set (match_operand:IMSA 0 "register_operand") + (minus:IMSA (match_dup 2) + (match_operand:IMSA 1 "register_operand")))] "ISA_HAS_MSA" { rtx reg = gen_reg_rtx (mode); @@ -607,6 +611,14 @@ operands[2] = reg; }) +(define_insn "neg2" + [(set (match_operand:FMSA 0 "register_operand" "=f") + (neg (match_operand:FMSA 1 "register_operand" "f")))] + "ISA_HAS_MSA" + "bnegi.\t%w0,%w1," + [(set_attr "type" "simd_bit") + (set_attr "mode" "")]) + (define_expand "msa_ldi" [(match_operand:IMSA 0 "register_operand") (match_operand 1 "const_imm10_operand")]