From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1944) id 07007385E451; Wed, 14 Feb 2024 15:36:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 07007385E451 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1707924978; bh=kFx7dY0/ATXkyktyvTQ8BQjj0BrlDc4XKw0QiIjeDKM=; h=From:To:Subject:Date:From; b=Ke4DaN4B9FOCF8bd4Gy3kutNxn+nYzAH3kSkiCaYbR1HfTEn92uhCYXr20jNYlyF7 I9mr1JXzIdsjbOunfl7reKBtnrl4q1tjRMENb93eHhk6PkEpjMrMZLEmf8QWBkWwzi wYYimUgEp828to28WUe4XTUqdYRYN2E5e+vFIxrI= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Szabolcs Nagy To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/ARM/heads/gcs-13)] aarch64: Add march flags for +the and +d128 arch extensions X-Act-Checkin: gcc X-Git-Author: Victor Do Nascimento X-Git-Refname: refs/vendors/ARM/heads/gcs-13 X-Git-Oldrev: 4a7f41222a71f75d56c1111b6b0ffc19436c89d9 X-Git-Newrev: 33bfcdbe6939603c7832832f19400024ec08e8ed Message-Id: <20240214153618.07007385E451@sourceware.org> Date: Wed, 14 Feb 2024 15:36:17 +0000 (GMT) List-Id: https://gcc.gnu.org/g:33bfcdbe6939603c7832832f19400024ec08e8ed commit 33bfcdbe6939603c7832832f19400024ec08e8ed Author: Victor Do Nascimento Date: Wed May 3 12:02:54 2023 +0100 aarch64: Add march flags for +the and +d128 arch extensions Given the introduction of optional 128-bit page table descriptor and translation hardening extension support with the Arm9.4-a architecture, this introduces the relevant flags to enable the reading and writing of 128-bit system registers. The `+d128' -march modifier enables the use of the following ACLE builtin functions: * __uint128_t __arm_rsr128(const char *special_register); * void __arm_wsr128(const char *special_register, __uint128_t value); and defines the __ARM_FEATURE_SYSREG128 macro to 1. Finally, the `rcwmask_el1' and `rcwsmask_el1' 128-bit system register implementations are also reliant on the enablement of the `+the' flag, which is thus also implemented in this patch. gcc/ChangeLog: * config/aarch64/aarch64-c.cc (__ARM_FEATURE_SYSREG128): New. * config/aarch64/aarch64-arches.def (armv8.9-a): New. (armv9.4-a): Likewise. * config/aarch64/aarch64-option-extensions.def (d128): Likewise. (the): Likewise. * config/aarch64/aarch64.h (AARCH64_ISA_V9_4A): Likewise. (AARCH64_ISA_V8_9A): Likewise. (TARGET_ARMV9_4): Likewise. (AARCH64_ISA_D128): Likewise. (AARCH64_ISA_THE): Likewise. (TARGET_D128): Likewise. * doc/invoke.texi (AArch64 Options): Document new -march flags and extensions. (cherry picked from commit 16a05fac33ddde7a50da9cb937a9b83ea7c111f6) Heavily modified when merged. Diff: --- gcc/config/aarch64/aarch64-arches.def | 2 ++ gcc/config/aarch64/aarch64.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/gcc/config/aarch64/aarch64-arches.def b/gcc/config/aarch64/aarch64-arches.def index 7ae92aa8e984..becccb801d02 100644 --- a/gcc/config/aarch64/aarch64-arches.def +++ b/gcc/config/aarch64/aarch64-arches.def @@ -39,10 +39,12 @@ AARCH64_ARCH("armv8.5-a", generic, V8_5A, 8, (V8_4A, SB, SSBS, PR AARCH64_ARCH("armv8.6-a", generic, V8_6A, 8, (V8_5A, I8MM, BF16)) AARCH64_ARCH("armv8.7-a", generic, V8_7A, 8, (V8_6A, LS64)) AARCH64_ARCH("armv8.8-a", generic, V8_8A, 8, (V8_7A, MOPS)) +AARCH64_ARCH("armv8.9-a", generic, V8_9A, 8, (V8_8A)) AARCH64_ARCH("armv8-r", generic, V8R , 8, (V8_4A)) AARCH64_ARCH("armv9-a", generic, V9A , 9, (V8_5A, SVE2)) AARCH64_ARCH("armv9.1-a", generic, V9_1A, 9, (V8_6A, V9A)) AARCH64_ARCH("armv9.2-a", generic, V9_2A, 9, (V8_7A, V9_1A)) AARCH64_ARCH("armv9.3-a", generic, V9_3A, 9, (V8_8A, V9_2A)) +AARCH64_ARCH("armv9.4-a", generic, V9_4A, 9, (V8_9A, V9_3A)) #undef AARCH64_ARCH diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 114c4edea45b..bd2650191dea 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -219,6 +219,7 @@ enum class aarch64_feature : unsigned char { #define AARCH64_ISA_V9_1A (aarch64_isa_flags & AARCH64_FL_V9_1A) #define AARCH64_ISA_V9_2A (aarch64_isa_flags & AARCH64_FL_V9_2A) #define AARCH64_ISA_V9_3A (aarch64_isa_flags & AARCH64_FL_V9_3A) +#define AARCH64_ISA_V9_4A (aarch64_isa_flags & AARCH64_FL_V9_4A) #define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS) #define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64) #define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC) @@ -366,6 +367,9 @@ enum class aarch64_feature : unsigned char { /* ARMv8.1-A Adv.SIMD support. */ #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA) +/* Armv9.4-A features. */ +#define TARGET_ARMV9_4 (AARCH64_ISA_V9_4A) + /* Standard register usage. */ /* 31 64-bit general purpose registers R0-R30: