From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1944) id 1FB18385E44E; Wed, 14 Feb 2024 15:36:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1FB18385E44E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1707924983; bh=IbEBvGT9DX0tvslYZn8mb2IY6bIiLhMI0zWrQyD/Yrk=; h=From:To:Subject:Date:From; b=nw9WMTw1sSG9XQHXsbxhFiFI2FyDHKzd1HBH3p3wXho/pRreGN0XWHW6OjKDjP8Lp 5c33117G8b64q03+cv01fEL7zb5wacUuhz71x0Dv0T7ytNswyhgdzsOLg8wJs3MpNe k2zCMEMPM22dGr0BCMr5bDKZTL9L6LZMSPQKzhBg= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Szabolcs Nagy To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/ARM/heads/gcs-13)] aarch64: Add support for GCS system registers with the +gcs modifier X-Act-Checkin: gcc X-Git-Author: Victor Do Nascimento X-Git-Refname: refs/vendors/ARM/heads/gcs-13 X-Git-Oldrev: 33bfcdbe6939603c7832832f19400024ec08e8ed X-Git-Newrev: 6ce354816bcb27658973e0081ebb5e6dd967a79f Message-Id: <20240214153623.1FB18385E44E@sourceware.org> Date: Wed, 14 Feb 2024 15:36:23 +0000 (GMT) List-Id: https://gcc.gnu.org/g:6ce354816bcb27658973e0081ebb5e6dd967a79f commit 6ce354816bcb27658973e0081ebb5e6dd967a79f Author: Victor Do Nascimento Date: Fri Nov 3 16:44:56 2023 +0000 aarch64: Add support for GCS system registers with the +gcs modifier Given the introduction of system registers associated with the Guarded Control Stack extension to Armv9.4-a in Binutils and their reliance on the `+gcs' modifier, we implement the necessary changes in GCC to allow for them to be recognized by the compiler. gcc/ChangeLog: * config/aarch64/aarch64-option-extensions.def (gcs): New. * config/aarch64/aarch64.h (AARCH64_ISA_GCS): New. (TARGET_THE): Likewise. * doc/invoke.texi (AArch64 Options): Describe GCS. (cherry picked from commit 3aba045882d1f589d36eaedd947a014ac6eb5ec3) Modified when merged. Diff: --- gcc/config/aarch64/aarch64-option-extensions.def | 2 ++ gcc/config/aarch64/aarch64.h | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index 825f3bf77589..2749bab3005d 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -151,4 +151,6 @@ AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "") AARCH64_OPT_EXTENSION("cssc", CSSC, (), (), (), "cssc") +AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs") + #undef AARCH64_OPT_EXTENSION diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index bd2650191dea..cece9cd2651f 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -223,6 +223,7 @@ enum class aarch64_feature : unsigned char { #define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS) #define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64) #define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC) +#define AARCH64_ISA_GCS (aarch64_isa_flags & AARCH64_FL_GCS) /* Crypto is an optional extension to AdvSIMD. */ #define TARGET_CRYPTO (AARCH64_ISA_CRYPTO) @@ -370,6 +371,10 @@ enum class aarch64_feature : unsigned char { /* Armv9.4-A features. */ #define TARGET_ARMV9_4 (AARCH64_ISA_V9_4A) +/* Armv9.4-A Guarded Control Stack extension system registers are + enabled through +gcs. */ +#define TARGET_GCS (AARCH64_ISA_GCS) + /* Standard register usage. */ /* 31 64-bit general purpose registers R0-R30: