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From: Szabolcs Nagy <nsz@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/ARM/heads/gcs-13)] aarch64: Add support for chkfeat insn Date: Wed, 14 Feb 2024 15:36:58 +0000 (GMT) [thread overview] Message-ID: <20240214153659.057763860001@sourceware.org> (raw) https://gcc.gnu.org/g:3f9cbc30f61e8708ad8e691934a9f978af837501 commit 3f9cbc30f61e8708ad8e691934a9f978af837501 Author: Szabolcs Nagy <szabolcs.nagy@arm.com> Date: Tue May 9 15:37:49 2023 +0100 aarch64: Add support for chkfeat insn This is a hint space instruction to check for enabled HW features and update the x16 register accordingly. Use unspec_volatile to prevent reordering it around calls since calls can enable or disable HW features. gcc/ChangeLog: * config/aarch64/aarch64.md (aarch64_chkfeat): New. Diff: --- gcc/config/aarch64/aarch64.md | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index d0b9f1ced7e8..de7481bd3c72 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -319,6 +319,7 @@ UNSPECV_BTI_C ; Represent BTI c. UNSPECV_BTI_J ; Represent BTI j. UNSPECV_BTI_JC ; Represent BTI jc. + UNSPECV_CHKFEAT ; Represent CHKFEAT X16. UNSPECV_TSTART ; Represent transaction start. UNSPECV_TCOMMIT ; Represent transaction commit. UNSPECV_TCANCEL ; Represent transaction cancel. @@ -7897,6 +7898,14 @@ [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))] ) +;; CHKFEAT instruction +(define_insn "aarch64_chkfeat" + [(set (reg:DI R16_REGNUM) + (unspec_volatile:DI [(reg:DI R16_REGNUM)] UNSPECV_CHKFEAT))] + "" + "hint\\t40 // chkfeat x16" +) + ;; AdvSIMD Stuff (include "aarch64-simd.md")
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