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From: Szabolcs Nagy <nsz@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/ARM/heads/gcs-13)] aarch64: Add __builtin_aarch64_chkfeat Date: Wed, 14 Feb 2024 15:37:04 +0000 (GMT) [thread overview] Message-ID: <20240214153704.1DC6E385E83F@sourceware.org> (raw) https://gcc.gnu.org/g:8e623cab64d6b4b2d18ab8c3983ec4cca723cfe8 commit 8e623cab64d6b4b2d18ab8c3983ec4cca723cfe8 Author: Szabolcs Nagy <szabolcs.nagy@arm.com> Date: Tue May 9 15:24:18 2023 +0100 aarch64: Add __builtin_aarch64_chkfeat Builtin for chkfeat: the input argument is used to initialize x16 then execute chkfeat and return the updated x16. Note: ACLE __chkfeat(x) plans to flip the bits to be more intuitive (xor the input to output), but for the builtin that seems unnecessary complication. gcc/ChangeLog: * config/aarch64/aarch64-builtins.cc (enum aarch64_builtins): Define AARCH64_BUILTIN_CHKFEAT. (aarch64_general_init_builtins): Handle chkfeat. (aarch64_general_expand_builtin): Handle chkfeat. Diff: --- gcc/config/aarch64/aarch64-builtins.cc | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index dd9f11501657..cff7836e9480 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -785,6 +785,8 @@ enum aarch64_builtins AARCH64_RBIT, AARCH64_RBITL, AARCH64_RBITLL, + /* Armv8.9-A / Armv9.4-A builtins. */ + AARCH64_BUILTIN_CHKFEAT, AARCH64_BUILTIN_MAX }; @@ -2017,6 +2019,12 @@ aarch64_general_init_builtins (void) if (TARGET_MEMTAG) aarch64_init_memtag_builtins (); + tree ftype_chkfeat + = build_function_type_list (uint64_type_node, uint64_type_node, NULL); + aarch64_builtin_decls[AARCH64_BUILTIN_CHKFEAT] + = aarch64_general_add_builtin ("__builtin_aarch64_chkfeat", ftype_chkfeat, + AARCH64_BUILTIN_CHKFEAT); + if (in_lto_p) handle_arm_acle_h (); } @@ -2809,6 +2817,16 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target, case AARCH64_BUILTIN_RNG_RNDR: case AARCH64_BUILTIN_RNG_RNDRRS: return aarch64_expand_rng_builtin (exp, target, fcode, ignore); + + case AARCH64_BUILTIN_CHKFEAT: + { + rtx x16_reg = gen_rtx_REG (DImode, R16_REGNUM); + op0 = expand_normal (CALL_EXPR_ARG (exp, 0)); + emit_move_insn (x16_reg, op0); + expand_insn (CODE_FOR_aarch64_chkfeat, 0, 0); + emit_move_insn (target, x16_reg); + return target; + } } if (fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX)
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