[gcc r14-8991] testsuite: Fix a couple of x86 issues in gcc.dg/vect testsuite

[Uros Bizjak <uros@gcc.gnu.org>]

https://gcc.gnu.org/g:430c772be3382134886db33133ed466c02efc71c

commit r14-8991-g430c772be3382134886db33133ed466c02efc71c
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Wed Feb 14 21:09:35 2024 +0100

    testsuite: Fix a couple of x86 issues in gcc.dg/vect testsuite
    
    A compile-time test can use -march=skylake-avx512 for all x86 targets,
    but a runtime test needs to check avx512f effective target if the
    instructions can be assembled.
    
    The runtime test also needs to check if the target machine supports
    instruction set we have been compiled for.  The testsuite uses check_vect
    infrastructure, but handling of AVX512F+ ISAs was missing there.
    
    Add detection of __AVX512F__ and __AVX512VL__, which is enough to handle
    all currently mentioned target processors in the gcc.dg/vect testsuite.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.dg/vect/pr113576.c (dg-additional-options):
            Use -march=skylake-avx512 for avx512f effective target.
            * gcc.dg/vect/pr98308.c (dg-additional-options):
            Use -march=skylake-avx512 for all x86 targets.
            * gcc.dg/vect/tree-vect.h (check_vect): Handle __AVX512F__
            and __AVX512VL__.

Diff:
---
 gcc/testsuite/gcc.dg/vect/pr113576.c  | 2 +-
 gcc/testsuite/gcc.dg/vect/pr98308.c   | 2 +-
 gcc/testsuite/gcc.dg/vect/tree-vect.h | 6 +++++-
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/pr113576.c b/gcc/testsuite/gcc.dg/vect/pr113576.c
index decb7abe2f75..b6edde6f8e2c 100644
--- a/gcc/testsuite/gcc.dg/vect/pr113576.c
+++ b/gcc/testsuite/gcc.dg/vect/pr113576.c
@@ -1,6 +1,6 @@
 /* { dg-do run } */
 /* { dg-options "-O3" } */
-/* { dg-additional-options "-march=skylake-avx512" { target { x86_64-*-* i?86-*-* } } } */
+/* { dg-additional-options "-march=skylake-avx512" { target avx512f } } */
 
 #include "tree-vect.h"
 
diff --git a/gcc/testsuite/gcc.dg/vect/pr98308.c b/gcc/testsuite/gcc.dg/vect/pr98308.c
index aeec9771c553..d74431200c74 100644
--- a/gcc/testsuite/gcc.dg/vect/pr98308.c
+++ b/gcc/testsuite/gcc.dg/vect/pr98308.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-additional-options "-O3" } */
-/* { dg-additional-options "-march=skylake-avx512" { target avx512f } } */
+/* { dg-additional-options "-march=skylake-avx512" { target x86_64-*-* i?86-*-* } } */
 /* { dg-additional-options "-fdump-tree-optimized-details-blocks" } */
 
 extern unsigned long long int arr_86[];
diff --git a/gcc/testsuite/gcc.dg/vect/tree-vect.h b/gcc/testsuite/gcc.dg/vect/tree-vect.h
index c4b814412166..1e4b56ee0e15 100644
--- a/gcc/testsuite/gcc.dg/vect/tree-vect.h
+++ b/gcc/testsuite/gcc.dg/vect/tree-vect.h
@@ -38,7 +38,11 @@ check_vect (void)
     /* Determine what instruction set we've been compiled for, and detect
        that we're running with it.  This allows us to at least do a compile
        check for, e.g. SSE4.1 when the machine only supports SSE2.  */
-# if defined(__AVX2__)
+# if defined(__AVX512VL__)
+    want_level = 7, want_b = bit_AVX512VL;
+# elif defined(__AVX512F__)
+    want_level = 7, want_b = bit_AVX512F;
+# elif defined(__AVX2__)
     want_level = 7, want_b = bit_AVX2;
 # elif defined(__AVX__)
     want_level = 1, want_c = bit_AVX;