From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id D713A3857716; Wed, 14 Feb 2024 23:37:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D713A3857716 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1707953825; bh=GEzu8LVg2hBHi6w4Cj1ggjlb9ZjWBq3jrBbgVzgw1ks=; h=From:To:Subject:Date:From; b=owDay7NclK+EEuhiqwCmvJ7vv/PHq/H9NN+lVCS8Yeg6AG0GjyVfWq5iZvlkGxbsH AaI9tfLjRRDvYoGiCIWxfeEYZtL/84B43hEHaviFmytGozhLfGSlWTosTr0FfyQVQA 3SwPzOvfnPmka8TVCIo2tqgz8hRQzCv6EGQ3EBLo= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work158-pnext)] Update ChangeLog.* X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work158-pnext X-Git-Oldrev: 92de062ee20714e535363e0a926f99ff960a970d X-Git-Newrev: 48a4b5c7b4c0cca39c0ffe21192d4c2d1ec74a99 Message-Id: <20240214233705.D713A3857716@sourceware.org> Date: Wed, 14 Feb 2024 23:37:05 +0000 (GMT) List-Id: https://gcc.gnu.org/g:48a4b5c7b4c0cca39c0ffe21192d4c2d1ec74a99 commit 48a4b5c7b4c0cca39c0ffe21192d4c2d1ec74a99 Author: Michael Meissner Date: Wed Feb 14 18:36:55 2024 -0500 Update ChangeLog.* Diff: --- gcc/ChangeLog.pnext | 266 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 266 insertions(+) diff --git a/gcc/ChangeLog.pnext b/gcc/ChangeLog.pnext index 307f509e053c..b8ec896e9b93 100644 --- a/gcc/ChangeLog.pnext +++ b/gcc/ChangeLog.pnext @@ -1,5 +1,271 @@ +==================== Branch work158-pnext, patch #107 from work158-future branch ==================== + +Enable using vector pair load/store for -mcpu=future + +Late in the development of power10, we discovered that there were some issues +in using load vector pair and store vector pair instructions to do memory +copies, so the defaults were modified to not use these instructions. This +patch re-enables using load and store vector pair instructions. + +Previously the -mblock-ops-vector-pair switch was not set in POWERPC_MASKS. +This means the option was not reset if the cpu was changed via target +attributes or targt pragmas. I added this mask to POWERPC_MASKS since the +option is set via -mcpu=future. + +2024-02-14 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Turn on + -mblock-ops-vector-pair for -mcpu=future. + (POWERPC_MASKS): Add -mblock-ops-vector-pair. + +==================== Branch work158-pnext, patch #106 from work158-future branch ==================== + +Set future machine type in assembler if -mcpu=future + +This patch uses the .machine directive to tell the assembler to use any +possible future instructions. + +2024-02-14 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (rs6000_machine_from_flags): Output .machine + future if -mcpu=future. + +==================== Branch work158-pnext, patch #105 from work158-future branch ==================== + +Make -mtune=future be the same as -mtune=power10. + +This patch makes -mcpu=future act like -mcpu=power10 in terms of tuning. If +future patches changes the tuning, then this patch woucl be changed to use the +new tuning information. Until there is different tuning, this patch does not +allow the user to explicitly use -mtune=future. + +2024-02-14 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Make + -mtune=future become -mtune=power10. + +==================== Branch work158-pnext, patch #104 from work158-future branch ==================== + +Pass -mfuture to assembler if -mcpu=future. + +This patch passes -mfuture to the assembler if the user used -mcpu=future. + +2024-02-14 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.h (ASM_CPU_SPEC): If -mcpu=future, pass -mfuture + to the assembler. + +==================== Branch work158-pnext, patch #103 from work158-future branch ==================== + +Define _ARCH_PWR_FUTURE if -mcpu=future. + +This patch defines _ARCH_PWR_FUTURE if -mcpu=future was used. + +2024-02-14 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + +==================== Branch work158-pnext, patch #102 from work158-future branch ==================== + +Add debugging for -mcpu=future + +This patch prints that -mcpu=future was selected if you use the debugging +switch -mdebug=reg. + +2024-02-14 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (rs6000_opt_masks): Add entry to print out + -mfuture in the isa flags. + +==================== Branch work158-pnext, patch #101 from work158-future branch ==================== + +Add initial -mcpu=future support. + +This patch adds the basic support for -mcpu=future, which is a framework to add +support for possible future PowerPCs. This patch is only sets the future bit +in the ISA options. + +2024-02-14 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New option + bits for -mcpu=future. + (POWERPC_MASKS): Add -mfuture mask. + (future cpu): Add -mcpu=future. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): New processor type. + * config/rs6000/rs6000-tables.opt (rs6000_cpu_opt_value): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Likewise. + * config/rs6000/rs6000.opt (-mfuture): New insert mask for -mcpu=future. + * doc/invoke.texi (PowerPC options): Add -mcpu=future. + +==================== Branch work158-pnext, patch #2 from work158 branch ==================== + +PR target/112886, Add %S to print_operand for vector pair support. + +In looking at support for load vector pair and store vector pair for the +PowerPC in GCC, I noticed that we were missing a print_operand output modifier +if you are dealing with vector pairs to print the 2nd register in the vector +pair. + +If the instruction inside of the asm used the Altivec encoding, then we could +use the %L modifier: + + __vector_pair *p, *q, *r; + // ... + __asm__ ("vaddudm %0,%1,%2\n\tvaddudm %L0,%L1,%L2" + : "=v" (*p) + : "v" (*q), "v" (*r)); + +Likewise if we know the value to be in a tradiational FPR register, %L will +work for instructions that use the VSX encoding: + + __vector_pair *p, *q, *r; + // ... + __asm__ ("xvadddp %x0,%x1,%x2\n\txvadddp %L0,%L1,%L2" + : "=f" (*p) + : "f" (*q), "f" (*r)); + +But if have a value that is in a traditional Altivec register, and the +instruction uses the VSX encoding, %L will a value between 0 and 31, when it +should give a value between 32 and 63. + +This patch adds %S that acts like %x, except that it adds 1 to the +register number. + +This is version 2 of the patch. The only difference is I made the test case +simpler to read. + +I have tested this on power10 and power9 little endian systems and on a power9 +big endian system. There were no regressions in the patch. Can I apply it to +the trunk? + +It would be nice if I could apply it to the open branches. Can I backport it +after a burn-in period? + +2024-02-09 Michael Meissner + +gcc/ + + PR target/112886 + * config/rs6000/rs6000.cc (print_operand): Add %S output modifier. + * doc/md.texi (Modifiers): Mention %S can be used like %x. + +gcc/testsuite/ + + PR target/112886 + * /gcc.target/powerpc/pr112886.c: New test. + +==================== Branch work158-pnext, patch #1 from work158 branch ==================== + +Power10: Add options to disable load and store vector pair. + +This is version 2 of the patch to add -mno-load-vector-pair and +-mno-store-vector-pair undocumented tuning switches. + +The differences between the first version of the patch and this version is that +I added explicit RTL abi attributes for when the compiler can generate the load +vector pair and store vector pair instructions. By having this attribute, the +movoo insn has separate alternatives for when we generate the instruction and +when we want to split the instruction into 2 separate vector loads or stores. + +In the first version of the patch, I had previously provided built-in functions +that would always generate load vector pair and store vector pair instructions +even if these instructions are normally disabled. I found these built-ins +weren't specified like the other vector pair built-ins, and I didn't include +documentation for the built-in functions. If we want such built-in functions, +we can add them as a separate patch later. + +In addition, since both versions of the patch adds #pragma target and attribute +support to change the results for individual functions, we can select on a +function by function basis what the defaults for load/store vector pair is. + +The original text for the patch is: + +In working on some future patches that involve utilizing vector pair +instructions, I wanted to be able to tune my program to enable or disable using +the vector pair load or store operations while still keeping the other +operations on the vector pair. + +This patch adds two undocumented tuning options. The -mno-load-vector-pair +option would tell GCC to generate two load vector instructions instead of a +single load vector pair. The -mno-store-vector-pair option would tell GCC to +generate two store vector instructions instead of a single store vector pair. + +If either -mno-load-vector-pair is used, GCC will not generate the indexed +stxvpx instruction. Similarly if -mno-store-vector-pair is used, GCC will not +generate the indexed lxvpx instruction. The reason for this is to enable +splitting the {,p}lxvp or {,p}stxvp instructions after reload without needing a +scratch GPR register. + +The default for -mcpu=power10 is that both load vector pair and store vector +pair are enabled. + +I added code so that the user code can modify these settings using either a +'#pragma GCC target' directive or used __attribute__((__target__(...))) in the +function declaration. + +I added tests for the switches, #pragma, and attribute options. + +I have built this on both little endian power10 systems and big endian power9 +systems doing the normal bootstrap and test. There were no regressions in any +of the tests, and the new tests passed. Can I check this patch into the master +branch? + +2024-02-09 Michael Meissner + +gcc/ + + * config/rs6000/mma.md (movoo): Add support for -mno-load-vector-pair and + -mno-store-vector-pair. + * config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add support for + -mload-vector-pair and -mstore-vector-pair. + (POWERPC_MASKS): Likewise. + * config/rs6000/rs6000.cc (rs6000_setup_reg_addr_masks): Only allow + indexed mode for OOmode if we are generating both load vector pair and + store vector pair instructions. + (rs6000_option_override_internal): Add support for -mno-load-vector-pair + and -mno-store-vector-pair. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.md (isa attribute): Add lxvp and stxvp + attributes. + (enabled attribute): Likewise. + * config/rs6000/rs6000.opt (-mload-vector-pair): New option. + (-mstore-vector-pair): Likewise. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-pair-attribute.c: New test. + * gcc.target/powerpc/vector-pair-pragma.c: New test. + * gcc.target/powerpc/vector-pair-switch1.c: New test. + * gcc.target/powerpc/vector-pair-switch2.c: New test. + * gcc.target/powerpc/vector-pair-switch3.c: New test. + * gcc.target/powerpc/vector-pair-switch4.c: New test. + ==================== Branch work158-pnext, baseline ==================== +Add ChangeLog.pnext and update REVISION. + +2024-02-09 Michael Meissner + +gcc/ + + * ChangeLog.pnext: New file for branch. + * REVISION: Update. + 2024-02-09 Michael Meissner Clone branch