From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 72B0D384CBBE; Thu, 15 Feb 2024 23:49:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 72B0D384CBBE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1708040953; bh=TNYKUfKszZdTNu80+TD3PmOasUKoLFp+wGKaFL2mxQA=; h=From:To:Subject:Date:From; b=EaU9Py+uh98DSmmTuhhy9pGxkF2ZgB25UzbwB7ltgUot5PGgh5b1OvzzaxWzTUX1M KfNepi5ikROgsA9xIhJ51wEdA+nuDJQjJf32lLzQ7ThmhwiLASbIWZVUBcAR3AdaOv WdtsyWeJiErf/Ai2dlzQLiD9mPvwxc+ql3gCe/Tc= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work158-pnext)] Revert changes X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work158-pnext X-Git-Oldrev: 6526329c046dc37a2c592d7ba12f775300f2b361 X-Git-Newrev: 8240552b630646747ced4a12317fdd6e9764c5da Message-Id: <20240215234913.72B0D384CBBE@sourceware.org> Date: Thu, 15 Feb 2024 23:49:13 +0000 (GMT) List-Id: https://gcc.gnu.org/g:8240552b630646747ced4a12317fdd6e9764c5da commit 8240552b630646747ced4a12317fdd6e9764c5da Author: Michael Meissner Date: Thu Feb 15 18:49:09 2024 -0500 Revert changes Diff: --- gcc/ChangeLog.pnext | 141 +----------------------------------- gcc/config.gcc | 7 +- gcc/config/rs6000/rs6000-c.cc | 4 - gcc/config/rs6000/rs6000-cpus.def | 14 ---- gcc/config/rs6000/rs6000-opts.h | 4 - gcc/config/rs6000/rs6000-tables.opt | 6 -- gcc/config/rs6000/rs6000.cc | 6 -- gcc/config/rs6000/rs6000.h | 2 - gcc/config/rs6000/rs6000.opt | 6 -- gcc/doc/invoke.texi | 5 +- 10 files changed, 8 insertions(+), 187 deletions(-) diff --git a/gcc/ChangeLog.pnext b/gcc/ChangeLog.pnext index 422782f69f96..68de3ce18c85 100644 --- a/gcc/ChangeLog.pnext +++ b/gcc/ChangeLog.pnext @@ -1,143 +1,8 @@ -==================== Branch work158-pnext, patch #200 ==================== +==================== Branch work158-pnext, patch #200 was reverted ==================== -Add -mcpu=power11 support. +==================== Branch work158-pnext, patches #111-116 were reverted ==================== -2024-02-15 Michael Meissner - -gcc/ - - * config.gcc (powerpc*-*-*, rs6000-*-*): Add support for - --with-cpu=power11. - * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define - _ARCH_PWR11 if -mcpu=power11. - * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New macro. - (POWERPC_MASKS): Add -mcpu=power11 ISA bit. - (power11 cpu): New cpu target. - * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Define as - PROCESSOR_POWER10 for now. - * config/rs6000/rs6000-tables.optL: Regenerate. - * config/rs6000/rs6000.cc (rs6000_machine_from_flags): Set .machine - power11 if -mcpu=power11. - (rs6000_opt_masks): Add Power11. - * config/rs6000/rs6000.h (ASM_CPU_SPEC): Pass -mpower11 to the assembler - if -mcpu=power11. - * config/rs6000/rs6000.opt (-mpower11): Add ISA bit for power11. - * doc/invoke.texi (PowerPC options): Document -mcpu=power11. - -==================== Branch work158-pnext, patch #116 from work158-future branch ==================== - -Add configure support for PowerPC future. - -2024-02-15 Michael Meissner - -gcc/ - - * config.gcc (powerpc*-*-*, rs6000-*-*): Add support for - --with-cpu=future. - -==================== Branch work158-pnext, patch #115 from work158-future branch ==================== - -Enable using vector pair load/store for -mcpu=future - -Late in the development of power10, we discovered that there were some issues -in using load vector pair and store vector pair instructions to do memory -copies, so the defaults were modified to not use these instructions. This -patch re-enables using load and store vector pair instructions. - -Previously the -mblock-ops-vector-pair switch was not set in POWERPC_MASKS. -This means the option was not reset if the cpu was changed via target -attributes or targt pragmas. I added this mask to POWERPC_MASKS since the -option is set via -mcpu=future. - -2024-02-15 Michael Meissner - -gcc/ - - * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Turn on - -mblock-ops-vector-pair for -mcpu=future. - (POWERPC_MASKS): Add -mblock-ops-vector-pair. - -==================== Branch work158-pnext, patch #114 from work158-future branch ==================== - -Set future machine type in assembler if -mcpu=future - -This patch uses the .machine directive to tell the assembler to use any -possible future instructions. - -2024-02-15 Michael Meissner - -gcc/ - - * config/rs6000/rs6000.cc (rs6000_machine_from_flags): Output .machine - future if -mcpu=future. - -==================== Branch work158-pnext, patch #113 from work158-future branch ==================== - -Pass -mfuture to assembler if -mcpu=future. - -This patch passes -mfuture to the assembler if the user used -mcpu=future. - -2024-02-15 Michael Meissner - -gcc/ - - * config/rs6000/rs6000.h (ASM_CPU_SPEC): If -mcpu=future, pass -mfuture - to the assembler. - -==================== Branch work158-pnext, patch #112 from work158-future branch ==================== - -Define _ARCH_PWR_FUTURE if -mcpu=future. - -This patch defines _ARCH_PWR_FUTURE if -mcpu=future was used. - -2024-02-15 Michael Meissner - -gcc/ - - * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define - _ARCH_PWR_FUTURE if -mcpu=future. - -==================== Branch work158-pnext, patch #111 from work158-future branch ==================== - -Add initial -mcpu=future support. - -This patch adds the basic support for -mcpu=future, which is a framework to add -support for possible future PowerPCs. Until there are changes for a possible -future PowerPC, -mcpu=future and -mtune=future default to power10. An ISA bit -is set to denote possible future instructions are enabled. - -2024-02-15 Michael Meissner - -gcc/ - - * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New option - bits for -mcpu=future. - (POWERPC_MASKS): Add -mfuture mask. - (future cpu): Add -mcpu=future. - * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Map PROCESSOR_FUTURE - into PROCESSOR_POWER10 until there are differences that necessate a new - processor enumeration. - * config/rs6000/rs6000-tables.opt (rs6000_cpu_opt_value): Add future - variant. - * config/rs6000/rs6000.cc (rs6000_opt_masks): Add printing -mfuture if - -mdebug=reg is used. Do not allow it to be set with a target attribute - or pragma. - * config/rs6000/rs6000.opt (-mfuture): New ISA bit for -mcpu=future. - * doc/invoke.texi (PowerPC options): Document -mcpu=future. - -==================== Branch work158-pnext, patch #107 was reverted from work158-future branch ==================== - -==================== Branch work158-pnext, patch #106 was reverted from work158-future branch ==================== - -==================== Branch work158-pnext, patch #105 was reverted from work158-future branch ==================== - -==================== Branch work158-pnext, patch #104 was reverted from work158-future branch ==================== - -==================== Branch work158-pnext, patch #103 was reverted from work158-future branch ==================== - -==================== Branch work158-pnext, patch #102 was reverted from work158-future branch ==================== - -==================== Branch work158-pnext, patch #101 was reverted from work158-future branch ==================== +==================== Branch work158-pnext, patches #101-107 were reverted ==================== ==================== Branch work158-pnext, patch #2 from work158 branch ==================== diff --git a/gcc/config.gcc b/gcc/config.gcc index 421d2482d248..a0f9c6723083 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -530,8 +530,7 @@ powerpc*-*-*) extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h" extra_headers="${extra_headers} amo.h" case x$with_cpu in - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|\ - xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture) + xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500) cpu_is_64bit=yes ;; esac @@ -5555,8 +5554,8 @@ case "${target}" in eval "with_$which=405" ;; "" | common | native \ - | power[3456789] | power1[01] | power5+ | power6x \ - | powerpc | powerpc64 | powerpc64le | future \ + | power[3456789] | power10 | power5+ | power6x \ + | powerpc | powerpc64 | powerpc64le \ | rs64 \ | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \ | 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \ diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index d15bb85743c1..ce0b14a8d373 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -447,10 +447,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); if ((flags & OPTION_MASK_POWER10) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10"); - if ((flags & OPTION_MASK_POWER11) != 0) - rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11"); - if ((flags & OPTION_MASK_FUTURE) != 0) - rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 40c2b2917749..d28cc87eb2a1 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -88,15 +88,6 @@ | OPTION_MASK_POWER10 \ | OTHER_POWER10_MASKS) -/* Flags for a Power11 processor. */ -#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \ - | OPTION_MASK_POWER11) - -/* Flags for a potential future processor that may or may not be delivered. */ -#define ISA_FUTURE_MASKS_SERVER (ISA_POWER11_MASKS_SERVER \ - | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \ - | OPTION_MASK_FUTURE) - /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_P9_MINMAX) @@ -132,7 +123,6 @@ /* Mask of all options to set the default isa flags based on -mcpu=. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ - | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \ | OPTION_MASK_CMPB \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DFP \ @@ -144,9 +134,7 @@ | OPTION_MASK_FPRND \ | OPTION_MASK_LOAD_VECTOR_PAIR \ | OPTION_MASK_POWER10 \ - | OPTION_MASK_POWER11 \ | OPTION_MASK_P10_FUSION \ - | OPTION_MASK_FUTURE \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ @@ -279,5 +267,3 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS_SERVER) -RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index 1fe228dae296..33fd0efc936f 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -70,10 +70,6 @@ enum processor_type PROCESSOR_TITAN }; -/* Until there are changes for either -mcpu=future or -mcpu=power11, treat them - to be like -mcpu=power10. */ -#define PROCESSOR_POWER11 PROCESSOR_POWER10 -#define PROCESSOR_FUTURE PROCESSOR_POWER10 /* Types of costly dependences. */ enum rs6000_dependence_cost diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index 2c96e3aa1bd2..65f46709716f 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -197,9 +197,3 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55) EnumValue Enum(rs6000_cpu_opt_value) String(rs64) Value(56) -EnumValue -Enum(rs6000_cpu_opt_value) String(future) Value(57) - -EnumValue -Enum(rs6000_cpu_opt_value) String(power11) Value(58) - diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 39ec1ed9ab67..68a14c6f88a3 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -5944,10 +5944,6 @@ rs6000_machine_from_flags (void) /* Disable the flags that should never influence the .machine selection. */ flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL); - if ((flags & OPTION_MASK_FUTURE) != 0) - return "future"; - if ((flags & OPTION_MASK_POWER11) != 0) - return "power11"; if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0) return "power10"; if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0) @@ -24508,7 +24504,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true }, { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, - { "future", OPTION_MASK_FUTURE, false, false }, { "power10", OPTION_MASK_POWER10, false, true }, { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, @@ -24531,7 +24526,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "power9-misc", OPTION_MASK_P9_MISC, false, true }, { "power9-vector", OPTION_MASK_P9_VECTOR, false, true }, { "power10-fusion", OPTION_MASK_P10_FUSION, false, true }, - { "power11", OPTION_MASK_POWER11, false, false }, { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true }, { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true }, { "prefixed", OPTION_MASK_PREFIXED, false, true }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 5ad2adbdace5..2291fe8d3a34 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -107,7 +107,6 @@ to the assembler if -mpower9-vector was also used. */ #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ - mcpu=power11: -mpower11; \ mcpu=power10: -mpower10; \ mcpu=power9: -mpower9; \ mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \ @@ -164,7 +163,6 @@ mcpu=e5500: -me5500; \ mcpu=e6500: -me6500; \ mcpu=titan: -mtitan; \ - mcpu=future: -mfuture; \ !mcpu*: %{mpower9-vector: -mpower9; \ mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ mvsx: -mpower7; \ diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 144173613102..60b923f5e4b3 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -612,12 +612,6 @@ mrop-protect Target Var(rs6000_rop_protect) Init(0) Enable instructions that guard against return-oriented programming attacks. -mpower11 -Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>) - -mfuture -Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>) - mprivileged Target Var(rs6000_privileged) Init(0) Generate code that will run in privileged state. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 85747e04ec8a..71339b8b30fa 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -31090,9 +31090,8 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, -@samp{power9}, @samp{power10}, @samp{power11}, -@samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le}, -@samp{rs64}, @samp{future}, and @samp{native}. +@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64}, +@samp{powerpc64le}, @samp{rs64}, and @samp{native}. @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and @option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either