From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2140) id AEEDF3858C56; Mon, 19 Feb 2024 21:40:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AEEDF3858C56 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1708378859; bh=q4x2eIOFDHLByVZOtLFuXTV0hfXBNCc1qGb5gAcYSug=; h=From:To:Subject:Date:From; b=xUxvS6VrhLSYcXlZzV/uCefeJ3CELWF41NA8FoRFERWC8VS9k0/xMieLq5RPWk06K CAoyF2RWL7uzGYJnQL6tGAZ4PkhkuBaQfdfiZLlaFsmZYT52jg4oE2/dF+aFY1P0By B5jKqy7XgE7v6FzeHdV7nhyVj+MmrhzdlRV3RyaA= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Alexandre Oliva To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/aoliva/heads/testme)] RISC-V: Fix CTZ unnecessary sign extension [PR #106888] X-Act-Checkin: gcc X-Git-Author: Raphael Moreira Zinsly X-Git-Refname: refs/users/aoliva/heads/testme X-Git-Oldrev: 41af6ad83777f8ad09ae7103d49def03e5918416 X-Git-Newrev: e43981de901e14a3d672f26959100968cb941cad Message-Id: <20240219214059.AEEDF3858C56@sourceware.org> Date: Mon, 19 Feb 2024 21:40:59 +0000 (GMT) List-Id: https://gcc.gnu.org/g:e43981de901e14a3d672f26959100968cb941cad commit e43981de901e14a3d672f26959100968cb941cad Author: Raphael Moreira Zinsly Date: Mon Feb 19 18:03:03 2024 -0300 RISC-V: Fix CTZ unnecessary sign extension [PR #106888] Changes since v1: - Remove subreg from operand 1. -- >8 -- We were not able to match the CTZ sign extend pattern on RISC-V because it gets optimized to zero extend and/or to ANDI patterns. For the ANDI case, combine scrambles the RTL and generates the extension by using subregs. gcc/ChangeLog: PR target/106888 * config/riscv/bitmanip.md (disi2): Match with any_extend. (disi2_sext): New pattern to match with sign extend using an ANDI instruction. gcc/testsuite/ChangeLog: PR target/106888 * gcc.target/riscv/pr106888.c: New test. * gcc.target/riscv/zbbw.c: Check for ANDI. (imported from commit 9000da00dd70988f30d43806bae33b22ee6b9904) Diff: --- gcc/config/riscv/bitmanip.md | 13 ++++++++++++- gcc/testsuite/gcc.target/riscv/pr106888.c | 12 ++++++++++++ gcc/testsuite/gcc.target/riscv/zbbw.c | 1 + 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 7aa591689ba8..cc55ca133c3f 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -246,13 +246,24 @@ (define_insn "*disi2" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI + (any_extend:DI (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))] "TARGET_64BIT && TARGET_ZBB" "w\t%0,%1" [(set_attr "type" "bitmanip") (set_attr "mode" "SI")]) +;; A SImode clz_ctz_pcnt may be extended to DImode via subreg. +(define_insn "*disi2_sext" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (subreg:DI + (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")) 0) + (match_operand:DI 2 "const_int_operand")))] + "TARGET_64BIT && TARGET_ZBB && ((INTVAL (operands[2]) & 0x3f) == 0x3f)" + "w\t%0,%1" + [(set_attr "type" "bitmanip") + (set_attr "mode" "SI")]) + (define_insn "*di2" [(set (match_operand:DI 0 "register_operand" "=r") (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/gcc.target/riscv/pr106888.c b/gcc/testsuite/gcc.target/riscv/pr106888.c new file mode 100644 index 000000000000..77fb8e5b79c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr106888.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */ + +int +ctz (int i) +{ + int res = __builtin_ctz (i); + return res&0xffff; +} + +/* { dg-final { scan-assembler-times "ctzw" 1 } } */ +/* { dg-final { scan-assembler-not "andi" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c index 709743c3b680..f7b2b63853f4 100644 --- a/gcc/testsuite/gcc.target/riscv/zbbw.c +++ b/gcc/testsuite/gcc.target/riscv/zbbw.c @@ -23,3 +23,4 @@ popcount (int i) /* { dg-final { scan-assembler-times "clzw" 1 } } */ /* { dg-final { scan-assembler-times "ctzw" 1 } } */ /* { dg-final { scan-assembler-times "cpopw" 1 } } */ +/* { dg-final { scan-assembler-not "andi\t" } } */