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From: Alexandre Oliva <aoliva@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/aoliva/heads/testme)] RISC-V: Fix CTZ unnecessary sign extension [PR #106888] Date: Mon, 19 Feb 2024 21:50:59 +0000 (GMT) [thread overview] Message-ID: <20240219215059.DBC3F3858C98@sourceware.org> (raw) https://gcc.gnu.org/g:6231d68aeaf4d8e3c67cfe8b0f2133db5e2afb69 commit 6231d68aeaf4d8e3c67cfe8b0f2133db5e2afb69 Author: Raphael Moreira Zinsly <rzinsly@ventanamicro.com> Date: Mon Feb 19 18:03:03 2024 -0300 RISC-V: Fix CTZ unnecessary sign extension [PR #106888] Changes since v1: - Remove subreg from operand 1. -- >8 -- We were not able to match the CTZ sign extend pattern on RISC-V because it gets optimized to zero extend and/or to ANDI patterns. For the ANDI case, combine scrambles the RTL and generates the extension by using subregs. gcc/ChangeLog: PR target/106888 * config/riscv/bitmanip.md (<bitmanip_optab>disi2): Match with any_extend. (<bitmanip_optab>disi2_sext): New pattern to match with sign extend using an ANDI instruction. gcc/testsuite/ChangeLog: PR target/106888 * gcc.target/riscv/pr106888.c: New test. * gcc.target/riscv/zbbw.c: Check for ANDI. (cherry picked from commit 9000da00dd70988f30d43806bae33b22ee6b9904) Diff: --- gcc/config/riscv/bitmanip.md | 13 ++++++++++++- gcc/testsuite/gcc.target/riscv/pr106888.c | 12 ++++++++++++ gcc/testsuite/gcc.target/riscv/zbbw.c | 1 + 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 7aa591689ba8..cc55ca133c3f 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -246,13 +246,24 @@ (define_insn "*<bitmanip_optab>disi2" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI + (any_extend:DI (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))] "TARGET_64BIT && TARGET_ZBB" "<bitmanip_insn>w\t%0,%1" [(set_attr "type" "bitmanip") (set_attr "mode" "SI")]) +;; A SImode clz_ctz_pcnt may be extended to DImode via subreg. +(define_insn "*<bitmanip_optab>disi2_sext" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (subreg:DI + (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")) 0) + (match_operand:DI 2 "const_int_operand")))] + "TARGET_64BIT && TARGET_ZBB && ((INTVAL (operands[2]) & 0x3f) == 0x3f)" + "<bitmanip_insn>w\t%0,%1" + [(set_attr "type" "bitmanip") + (set_attr "mode" "SI")]) + (define_insn "*<bitmanip_optab>di2" [(set (match_operand:DI 0 "register_operand" "=r") (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/gcc.target/riscv/pr106888.c b/gcc/testsuite/gcc.target/riscv/pr106888.c new file mode 100644 index 000000000000..77fb8e5b79c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr106888.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64" } */ + +int +ctz (int i) +{ + int res = __builtin_ctz (i); + return res&0xffff; +} + +/* { dg-final { scan-assembler-times "ctzw" 1 } } */ +/* { dg-final { scan-assembler-not "andi" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbbw.c b/gcc/testsuite/gcc.target/riscv/zbbw.c index 709743c3b680..f7b2b63853f4 100644 --- a/gcc/testsuite/gcc.target/riscv/zbbw.c +++ b/gcc/testsuite/gcc.target/riscv/zbbw.c @@ -23,3 +23,4 @@ popcount (int i) /* { dg-final { scan-assembler-times "clzw" 1 } } */ /* { dg-final { scan-assembler-times "ctzw" 1 } } */ /* { dg-final { scan-assembler-times "cpopw" 1 } } */ +/* { dg-final { scan-assembler-not "andi\t" } } */
next reply other threads:[~2024-02-19 21:50 UTC|newest] Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-19 21:50 Alexandre Oliva [this message] -- strict thread matches above, loose matches on Subject: below -- 2024-02-20 4:59 Alexandre Oliva 2024-02-19 21:40 Alexandre Oliva
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