From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id E1913385840E; Wed, 21 Feb 2024 18:35:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E1913385840E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1708540553; bh=yRfbE8WMtv8CKXCr9qM1yqTOgQsQZsHv+s0+MuwsiuM=; h=From:To:Subject:Date:From; b=UMNUiUIRMw19Q0aUsDKpbw7D69sxvMBV3qf/taEtZMD4Vbskk5XITCgTjgyopWWgE eP1y3aRUUfy5qk3wj66GdUMEFezCt1QWSYvUVZz0m7biS3HD2vDj2pdyDZnArp3nkZ tgNVEJlXiDhVGz7DUXsH15cN/iIoW/J3awkxHS6k= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work159)] Revert changes X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work159 X-Git-Oldrev: 714d4da4e751ec9f23b427997a15257ed9484ae4 X-Git-Newrev: d4834d2c67b92792080f289185382f11249c1f14 Message-Id: <20240221183553.E1913385840E@sourceware.org> Date: Wed, 21 Feb 2024 18:35:53 +0000 (GMT) List-Id: https://gcc.gnu.org/g:d4834d2c67b92792080f289185382f11249c1f14 commit d4834d2c67b92792080f289185382f11249c1f14 Author: Michael Meissner Date: Wed Feb 21 13:35:49 2024 -0500 Revert changes Diff: --- gcc/config.gcc | 7 +++---- gcc/config/rs6000/rs6000-c.cc | 4 ---- gcc/config/rs6000/rs6000-cpus.def | 13 ------------- gcc/config/rs6000/rs6000-opts.h | 4 ---- gcc/config/rs6000/rs6000-tables.opt | 6 ------ gcc/config/rs6000/rs6000.cc | 6 ------ gcc/config/rs6000/rs6000.h | 2 -- gcc/config/rs6000/rs6000.opt | 6 ------ gcc/doc/invoke.texi | 5 ++--- 9 files changed, 5 insertions(+), 48 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 421d2482d248..a0f9c6723083 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -530,8 +530,7 @@ powerpc*-*-*) extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h si2vmx.h" extra_headers="${extra_headers} amo.h" case x$with_cpu in - xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower1[01]|\ - xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture) + xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500) cpu_is_64bit=yes ;; esac @@ -5555,8 +5554,8 @@ case "${target}" in eval "with_$which=405" ;; "" | common | native \ - | power[3456789] | power1[01] | power5+ | power6x \ - | powerpc | powerpc64 | powerpc64le | future \ + | power[3456789] | power10 | power5+ | power6x \ + | powerpc | powerpc64 | powerpc64le \ | rs64 \ | 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \ | 476 | 476fp | 505 | 601 | 602 | 603 | 603e | ec603e \ diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index d15bb85743c1..ce0b14a8d373 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -447,10 +447,6 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); if ((flags & OPTION_MASK_POWER10) != 0) rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR10"); - if ((flags & OPTION_MASK_POWER11) != 0) - rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR11"); - if ((flags & OPTION_MASK_FUTURE) != 0) - rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR_FUTURE"); if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index e75321ddb838..276f3cdecaf1 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -86,14 +86,6 @@ | OPTION_MASK_POWER10 \ | OTHER_POWER10_MASKS) -/* Flags for a Power11 processor. */ -#define ISA_POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \ - | OPTION_MASK_POWER11) - -/* Flags for a potential future processor that may or may not be made. */ -#define ISA_FUTURE_MASKS_SERVER (ISA_POWER11_MASKS_SERVER \ - | OPTION_MASK_FUTURE) - /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_P9_MINMAX) @@ -129,7 +121,6 @@ /* Mask of all options to set the default isa flags based on -mcpu=. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ - | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \ | OPTION_MASK_CMPB \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DFP \ @@ -140,9 +131,7 @@ | OPTION_MASK_FLOAT128_KEYWORD \ | OPTION_MASK_FPRND \ | OPTION_MASK_POWER10 \ - | OPTION_MASK_POWER11 \ | OPTION_MASK_P10_FUSION \ - | OPTION_MASK_FUTURE \ | OPTION_MASK_HTM \ | OPTION_MASK_ISEL \ | OPTION_MASK_MFCRF \ @@ -274,5 +263,3 @@ RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 | ISA_POWER11_MASKS_SERVER) -RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 | ISA_FUTURE_MASKS_SERVER) diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h index 96a72c50c459..33fd0efc936f 100644 --- a/gcc/config/rs6000/rs6000-opts.h +++ b/gcc/config/rs6000/rs6000-opts.h @@ -70,10 +70,6 @@ enum processor_type PROCESSOR_TITAN }; -/* Until there are changes in instruction tuning for either power11 or a - possible future cpu, treat them to be like -mtune=power10. */ -#define PROCESSOR_POWER11 PROCESSOR_POWER10 -#define PROCESSOR_FUTURE PROCESSOR_POWER10 /* Types of costly dependences. */ enum rs6000_dependence_cost diff --git a/gcc/config/rs6000/rs6000-tables.opt b/gcc/config/rs6000/rs6000-tables.opt index f009c4e57186..65f46709716f 100644 --- a/gcc/config/rs6000/rs6000-tables.opt +++ b/gcc/config/rs6000/rs6000-tables.opt @@ -197,9 +197,3 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(55) EnumValue Enum(rs6000_cpu_opt_value) String(rs64) Value(56) -EnumValue -Enum(rs6000_cpu_opt_value) String(power11) Value(57) - -EnumValue -Enum(rs6000_cpu_opt_value) String(future) Value(58) - diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index b071541ea3a6..5d975dab9216 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -5920,10 +5920,6 @@ rs6000_machine_from_flags (void) /* Disable the flags that should never influence the .machine selection. */ flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL); - if ((flags & OPTION_MASK_FUTURE) != 0) - return "future"; - if ((flags & OPTION_MASK_POWER11) != 0) - return "power11"; if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0) return "power10"; if ((flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0) @@ -24480,7 +24476,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true }, { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, - { "future", OPTION_MASK_FUTURE, false, false }, { "power10", OPTION_MASK_POWER10, false, true }, { "hard-dfp", OPTION_MASK_DFP, false, true }, { "htm", OPTION_MASK_HTM, false, true }, @@ -24502,7 +24497,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "power9-misc", OPTION_MASK_P9_MISC, false, true }, { "power9-vector", OPTION_MASK_P9_VECTOR, false, true }, { "power10-fusion", OPTION_MASK_P10_FUSION, false, true }, - { "power11", OPTION_MASK_POWER11, false, false }, { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true }, { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true }, { "prefixed", OPTION_MASK_PREFIXED, false, true }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index f6025fbc6d67..2291fe8d3a34 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -107,8 +107,6 @@ to the assembler if -mpower9-vector was also used. */ #define ASM_CPU_SPEC \ "%{mcpu=native: %(asm_cpu_native); \ - mcpu=future: -mfuture; \ - mcpu=power11: -mpower11; \ mcpu=power10: -mpower10; \ mcpu=power9: -mpower9; \ mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \ diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 55527c15ed4b..5e32ee9b685d 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -604,12 +604,6 @@ mrop-protect Target Var(rs6000_rop_protect) Init(0) Enable instructions that guard against return-oriented programming attacks. -mpower11 -Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>) - -mfuture -Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) Warn(Do not use %<-mfuture>) - mprivileged Target Var(rs6000_privileged) Init(0) Generate code that will run in privileged state. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cd9eb2bb7b01..e18886e0ac7b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -31121,9 +31121,8 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403}, @samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8}, -@samp{power9}, @samp{power10}, @samp{power11}, -@samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le}, -@samp{rs64}, @samp{future}, and @samp{native}. +@samp{power9}, @samp{power10}, @samp{powerpc}, @samp{powerpc64}, +@samp{powerpc64le}, @samp{rs64}, and @samp{native}. @option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and @option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either